MSM56V16160F Просмотр технического описания (PDF) - Oki Electric Industry

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MSM56V16160F

2-Bank x 524,288 Word x 16 Bit SYNCHRONOUS DYNAMIC RAM

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MSM56V16160F

PIN DESCRIPTION

CLK

CS

CKE

Address

A11

RAS

CAS

WE

UDQM,

LDQM

DQi

Fetches all inputs at the “H” edge.

Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,

UDQM and LDQM.

Masks system clock to deactivate the subsequent CLK operation.

If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is

deactivated. CKE should be asserted at least one cycle prior to a new command.

Row & column multiplexed.

Row address : RA0 – RA10

Column Address : CA0 – CA7

Slects bank to be activated during row address latch time and selects bank for precharge and

read/write during column address latch time. A11=”L” : Bank A, A11=”H” : Bank B

Functionality depends on the combination. For details, see the function truth table.

Masks the read data of two clocks later when UDQM and LDQM are set “H” at the “H” edge of

the clock signal. Masks the write data of the same clock when UDQM and LDQM are set “H”

at the “H” edge of the clock signal. UDQM controls upper byte and LDQM controls lower byte.

Data inputs/outputs are multiplexed on the same pin.

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