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IDT49C466A

64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

Integrated Device Technology 

IDT49C466/A Flow-thruEDC™

ERROR DETECTION AND CORRECTION UNIT

COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION (Continued)

Pin Name

I/O

RBSEL

I

RBEN

I

RBREN

I

CBSEL

I

MEN

I

Clock Inputs

MCLK

I

SCLK

I

SYNCLK

I

Status Outputs

WBEF

O

WBFF

O

RBEF

O

RBHF

O

RBFF

O

ERR

O

MERR

O

PERR

O

Power Supply

VCC

P

GND

P

Description

Read FIFO Select: when HIGH, read FIFO is selected (data goes through read FIFO, not MD output

latch). When LOW, the MD output latch is selected.

Read FIFO Enable: when LOW, allows data to be written into the read FIFO on the LOW-to-HIGH

transition of the memory clock.

Read FIFO Enable: when LOW, allows data to be read from the read FIFO on the LOW-to-HIGH

transition of SCLK

Checkbit Syndrome Output Enable: Controls the CBSYN output buffer.When HIGH, the buffer is

enabled. When CBSEL is LOW, MOE controls the buffer.

Mode Enable Input: when LOW, SD0-15 is loaded into the EDC mode register on the LOW-to-HIGH

transition of the SCLK. This pin must be held LOW for the entire SCLK HIGH period, as shown in Figure

4.

Memory Clock: on the LOW-to-HIGH transition of MCLK, memory data is written to the read FIFO

when RBEN is LOW. Data is read from the write FIFO when WBREN is LOW, on the LOW-to-HIGH

transition of MCLK.

System Clock: on the LOW-to-HIGH transition of the SCLK, data is read from the read FIFO when

RBREN is LOW. Data on the system data bus is written into the write FIFO when WBEN is LOW on

the LOW-to-HIGH transition of SCLK. Clocks data into mode register when MEN is LOW.

Syndrome Clock: Used to load diagnostic registers. When an error occurs, Error Counter is

incremented on the rising SYNCLK edge (up to 15 errors). On the first error after a diagnostic reset,

SYNCLK rising edge clocks data into Check Bit, Syndrome, Error Type and Error Data registers. One

of the syndrome registers has new data clocked in on every SYNCLK rising edge.

Write FIFO Empty Flag: when LOW, indicates that the write FIFO is empty. After a reset, the WBEF

goes LOW.

Write FIFO Full Flag: when LOW, indicates that the write FIFO is full. After a reset, WBFF goes HIGH.

Read FIFO Empty Flag: when LOW, indicates that the read FIFO is empty. After a reset, the RBEF

goes LOW.

Read FIFO Half-full Flag: when LOW, indicates that there are eight or more data words (in the 16-

deep configuration) or four or more data words (in the dual 8-deep configuration) in the read FIFO. The

flag will return HIGH when less than eight (or four) data words are in the FIFO.

Read FIFO Full Flag: when LOW, indicates that the read FIFO is full. After a reset, RBFF goes HIGH.

Error Flag: when ERR is LOW, a data error is indicated. The ERR is not latched internally.

Multiple Error Flag: when MERR is LOW, a multiple data error is indicated. The MERR is not latched

internally.

Parity Error Flag: when LOW, indicates a parity error on the system data bus input.

Power Supply Voltage.

Ground.

2617 tbl 02

11.7

5

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