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IDT49C466PQF

64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

Integrated Device Technology 

IDT49C466/A Flow-thruEDC™

ERROR DETECTION AND CORRECTION UNIT

MODE BIT 0

CLEAR

COMMERCIAL TEMPERATURE RANGES

Diag. Regs.

Error Data Regs.

SYNCLK

64

WFIFO

BE0-7

BE0-7

WBSEL

Fig 3. Memory Initialization using Diagnostic Output/Error Data Output Mode

DIAGNOSTIC OUTPUT DATA FORMAT

TO SD BUS

37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8

Syndrome

(on every error)

Error

Type

(on

Error

Count

Syndrome

(on 1st error)

Checkbit

(on 1st error only)

1st

error

only)

7 6 54 32 10

Checkbit

(from checkbit latch)

* Bit #28 = 1 If "Error" condition

Bit #29 = 1 If "Multiple bit Error" condition FROM DIAGNOSTIC REGISTERS

Diagnostics

The diagnostic ability of the IDT49C466 rests on a set of 6

registers that provide error logging information. These include

the checkbit register, error count register, error type register,

2 syndrome registers and the error data register. Data is

clocked into each of these registers by SYNCLK. The error

data register, checkbit register, error type register and one of

the syndrome registers are reloaded only in the case of the

first error after a clear. The other syndrome register and the

error count register are reloaded on every error condition

SYNCLK edge. The contents of the Error Data register can be

read only in Error Data Output mode. The contents of the other

diagnostic registers as well as the checkbit latch can be read

in Diagnostic Output mode.

Parity

The IDT49C466 provides a parity check and generation

facility. On a memory read the EDC generates parity bits for

each data byte and outputs the parity byte on the parity bus,

P0-7. During a memory write, parity is checked by comparing

the parity bits input on P0-7 and the parity bits generated from

the input data word. A discrepancy between these two causes

the PERR flag to be asserted. In the case of partial word writes,

the PERR flag is based on the parity bits Px and data bytes

input on SD bus.

DIAG.

REGISTER

CHECKBIT

SYNDROME

(On 1st ERR)

ERR CNT

ERR TYPE

SYNDROME

(On every

ERROR)

LOADED

BY

SYNCLK ↑

SYNCLK ↑

SYNCLK ↑

SYNCLK ↑

SYNCLK ↑

2617 drw 07

CONDITION

OUTPUT

ONLY ON 1st

ERROR

ONLY ON 1st

ERROR

SD8-15

SD16-23

ON EVERY

ERROR (Up to

15 ERRORS)

SD24-27

ONLY ON 1st

ERROR

SD28-29

ON EVERY

ERROR

SD30-37

11.7

11

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