FEDR27V402E-01-03 Просмотр технического описания (PDF) - Oki Electric Industry
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FEDR27V402E-01-03 Datasheet PDF : 16 Pages
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OKI Semiconductor
FEDR27V402E-01-03
MR27V402E / OTP
BLOCK DIAGRAM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A–1
× 8/× 16 Switch
CE
OE
BYTE/VPP
CE
OE
PGM
Memory Cell Matrix
262,144 × 16-Bit or 524,288 × 8-Bit
Multiplexer
Output Buffer
D0 D2 D4 D6 D8 D10 D12 D14
D1 D3 D5 D7 D9 D11 D13 D15
In 8-bit output mode, these pins
are placed in a high-Z state and
pin D15 functions as the A-1
address pin.
FUNCTION TABLE
Mode
Read (16-Bit)
Read (8-Bit)
Output disable
CE
OE
L
L
L
L
L
H
Standby
Program
Program inhibit
Program verify
H
∗
L
H
H
H
H
L
∗: Don’t Care (H or L)
BYTE
H
L
H
L
H
L
9.75 V
VCC
3.3 V
4.0 V
D0 to D7
DOUT
D8 to D14
DOUT
Hi–Z
Hi–Z
Hi–Z
DIN
Hi–Z
DOUT
D15/A–1
L/H
∗
∗
3/16
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