MPC953FA Просмотр технического описания (PDF) - Motorola => Freescale

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MPC953FA

Low Voltage PLL Clock Driver

Motorola => Freescale 

MPC953

DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

VIH

Input HIGH Voltage LVCMOS Inputs

2.0

3.6

V

VIL

VPP

VCMR

Input LOW Voltage LVCMOS Inputs

Peak–to–Peak Input Voltage PECL_CLK

Common Mode Range

PECL_CLK

300

VCC–1.5

0.8

V

1000

mV

VCC–0.6 mV Note 1.

VOH

Output HIGH Voltage

2.4

V

IOH = –40mA, Note 2.

VOL

Output LOW Voltage

0.5

V

IOL = 40mA, Note 2.

IIN

Input Current

±120

µA

CIN

Input Capacitance

4

pF

Cpd

Power Dissipation Capacitance

25

pF Per Output

ICC

Maximum Quiescent Supply Current

75

mA All VCC Pins

ICCPLL

Maximum PLL Supply Current

15

20

mA VCCA Pin Only

1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within

the VCMR range and the input swing lies within the VPP specification.

2. The MPC953 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications

Info section).

PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)

Symbol

Characteristic

Min

Max

fref

Reference Input Frequency

Note 3.

Note 3.

frefDC

Reference Input Duty Cycle

25

75

3. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.

Unit

MHz

%

Condition

AC CHARACTERISTICS (TA = 0°C to 70°C, VCC = 3.3V ±5%)

Symbol

Characteristic

Min

Typ

Max

tr, tf

tpw

tsk(O)

fVCO

fmax

tpd(lock)

Output Rise/Fall Time

Output Duty Cycle

Output–to–Output Skews (Relative to QFB)

PLL VCO Lock Range

Maximum Output Frequency

Input to Ext_FB Delay (with PLL Locked)

0.10

45

200

50

X–100

50

X

(Note 4.)

1.0

55

±75

350

87.5

X+100

tpd(bypass) Input to Q Delay (with PLL Bypassed)

5

10

tPLZ,HZ

Output Disable Time

7

tPZL

Output Enable Time

6

tjitter

Cycle–to–Cycle Jitter (Peak–to–Peak)

100

tlock

Maximum PLL Lock Time

10

4. X will be targeted for 0ns, but may vary from target by ±150ps based on characterization of silicon.

Unit

ns

%

ps

MHz

MHz

ps

Condition

0.8 to 2.0V

VCO_SEL = ‘0’

fref = 75MHz

ns

ns

ns

ps

ms

ECLinPS and ECLinPS Lite

3

DL140 — Rev 3

MOTOROLA

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