MPC9443 Просмотр технического описания (PDF) - Motorola => Freescale
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MPC9443 Datasheet PDF : 16 Pages
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MPC9443
Freescale Semiconductor, Inc.
APPLICATIONS INFORMATION
Driving Transmission Lines
The MPC9443 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20Ω the
drivers can drive either parallel or series terminated
transmission lines at VCC = 3.3V. For more information on
transmission lines the reader is referred to application note
AN1091. In most high performance clock networks
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC÷2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9443 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 3. “Single
versus Dual Transmission Lines” illustrates an output driving
a single series terminated line versus two series terminated
lines in parallel. When taken to its extreme the fanout of the
MPC9443 clock driver is effectively doubled due to its
capability to drive multiple lines (at VCC = 3.3V).
MPC9443
OUTPUT
BUFFER
IN
19Ω
RS = 31Ω ZO = 50Ω
OutA
MPC9443
OUTPUT
BUFFER
IN
19Ω
RS = 31Ω ZO = 50Ω
RS = 31Ω ZO = 50Ω
OutB0
OutB1
Figure 3. Single versus Dual Transmission Lines
The waveform plots in Figure 4. “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC9443 output buffer is more than
sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC9443. The output waveform in Figure 4. “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 31Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
VL = VS ( Z0 ÷ (RS+R0 +Z0))
Z0 = 50Ω || 50Ω
RS = 31Ω || 31Ω
R0 = 19Ω
VL = 3.0 ( 25 ÷ (15.5+19+25)
= 1.26V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.52V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
3.0
OutA
2.5
tD = 3.8956
2.0
In
1.5
OutB
tD = 3.9386
1.0
0.5
0
2
4
6
8
10 12 14
TIME (nS)
Figure 4. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 5. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is perfectly
matched.
MPC9443
OUTPUT
BUFFER
19Ω
RS = 12Ω ZO = 50Ω
RS = 12Ω ZO = 50Ω
19Ω + 12Ω k 12Ω = 50Ω k 50Ω
25Ω = 25Ω
Figure 5. Optimized Dual Line Termination
MOTOROLA
For More Informa8tion On This Product,
Go to: www.freescale.com
TIMING SOLUTIONS
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