MP7613AG Просмотр технического описания (PDF) - Exar Corporation
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MP7613AG Datasheet PDF : 16 Pages
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MP7613
Data
1
Input/Output
Bus
0
Address 1
A0-A2
0
Chip Select 1
CS
0
Load Latch A 1
LD1
0
Load Latch B 1
LD2
0
+FS
Analog Output
–FS
don’t care
tAS
tCS1
tDS
tDH
tLD1W
tAH
tCH1
tLD1LD2
tLD2W
don’t care
tSD
Figure 1. Loading Latch A and Updating Latch B
Notes
(1) Chip Select (CS) and Load LATCHA (LD1) Signals follow the same timing constraints and are interchangeable
in the above diagram.
(2) R1 = R2 = 1.
(3) For the case where LD2 is in the low state, analog output would respond to the falling edge of LD1 (transparent mode).
Address
1
A0-A2
0
Chip Select
1
CS
0
Data Readback 1
RD
0
Digital Output Data 1
D0 to D13
0
tAS
tAH
don’t care
tCS2
HIGH-Z
tRD
tDA
tCH2
tDR
don’t care
HIGH-Z
Figure 2. Read Back First Latch Bank of One DAC
Notes
(1) Chip Select (CS) and Data Readback (RD) Signals follow the same timing constraints and are interchangeable
in the above diagram.
(2) R1 = R2 = 1.
1
R1
0
Reset first latch bank to
1000 . . . . .0000
tR1W
R2
1
0
Reset second latch bank to 1000 . . . . .0000 and analog
output to zero volt.
Figure 3. Reset Operations
Rev. 2.00
7
tR2W
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