CXD2307 Просмотр технического описания (PDF) - Sony Semiconductor
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CXD2307 Datasheet PDF : 15 Pages
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Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
AVss 49
RO 50
RO 51
AVDD 52
AVDD 53
GO 54
GO 55
AVDD 56
AVDD 57
BO 58
BO 59
AVDD 60
AVDD 61
DVDD 62
(LSB) R0 63
R1 64
32 GCK
31 RCK
30 CE
29 BLK
28 B9
27 B8
26 B7
25 B6
24 B5
23 B4
22 B3
21 B2
20 B1
19 B0 (LSB)
18 G9
17 G8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CXD2307R
Pin Description and Equivalent Circuit
Pin No.
Symbol I/O
63 to 8
9 to 18
19 to 28
R0 to R9
G0 to G9
B0 to B9
Equivalent circuit
29
BLK
DVDD
63
to
I
33
30
CE
DVSS
31
RCK
32
GCK
33
BCK
34
DVSS
—
—3—
Description
Digital input.
R0 (LSB) to R9 (MSB)
G0 (LSB) to G9 (MSB)
B0 (LSB) to B9 (MSB)
Blanking input.
This is synchronized with the clock
input signal for each channel.
No signal for High (0 V output).
Output generated for Low.
Chip enable pin.
This is not synchronized with the clock
input signal.
No signal at for High (0 V output) to
minimize power consumption.
Clock input.
Digital ground.
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