MK1418S Просмотр технического описания (PDF) - Integrated Circuit Systems
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MK1418S Datasheet PDF : 4 Pages
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MK1418/MK1420
OPL3, OPL4 + Codec Clock Source
Pin Assignments
Suggested Layout
for MK1420
clock only
ICLK
VDD
GND
16.9M
MK1418
1
8
2
7
3
6
4
5
GND
VDD
GND
24.6M
X1
VDD
GND
16.9M
MK1420
1
8
2
7
3
6
4
5
X2
14.3M
33.9M
24.6M
V
0.1µF
G
14.318 MHz
crystal
Pin 1 8
27
36
4
5
14.3MHz out
33Ω (optional)
33.9MHz out
33Ω (optional)
33Ω (optional)
33Ω (optional)
16.9MHz out 24.6MHz out
Pin Descriptions for MK1420
Number
1
2
3
4
5
6
7
8
Name
X1
VDD
GND
16.9M
24.6M
33.9M
14.3M
X2
Type
I
P
P
O
O
O
O
O
Description
Crystal Connection. Connect to a 14.318 MHz crystal or clock.
Connect to +5V.
Connect to ground.
16.9344 MHz clock output for stereo codec.
24.576 MHz clock output for stereo codec.
33.868 MHz clock output for OPL4.
14.318 MHz clock buffered output for OPL3 or PCMCIA controller.
Crystal Connection to a 14.318 MHz crystal, or leave unconnected for clock input.
Key: I = Input, O = output, P = power supply connection
External Components/Crystal Selection
A minimum number of external components are required for proper oscillation. For a crystal input, one
22pF load capacitor should be connected to each of the X1 and X2 pins and ground, and a parallel
resonant 14.318 MHz, 16pF load, crystal is recommended. Values near these are acceptable, as is a series
resonant crystal, but either will result in frequencies which are slightly (up to 0.06%) different from the
ideal. For a clock input, connect to X1 and leave X2 unconnected. A decoupling capacitor of 0.1µF should
be connected between VDD and GND, and 33Ω terminating resistors may be used on the clock outputs.
These terminating resistors are unnecessary for clock traces less than 1” (25mm).
MDS 1418/20 A
2
Revision 013098
Printed 11/15/00
MicroClock Division of ICS•1271 Parkmoor Ave.•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax
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