MIC2568 Просмотр технического описания (PDF) - Master Instrument Corporation
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MIC2568 Datasheet PDF : 10 Pages
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MIC2568
Output Timing Diagrams
A
VPP
Enable
0
VPP to 3.3V
VPP
OUT
5V
3.3V
t3
t1
B
C
VPP
OFF
VPP to 5V
t5
t7
t2
t4
D
VPP
OFF
t6
t8
Micrel
0
Figure 1. VPP Timing Diagram
VPP EN is shown generically. RL = 100Ω. Load capacitance is negligible. Refer to “MIC2568-0 Logic Table” for specific control
logic input.
At time A) VPP = 3.3V, B) VPP is disabled, C) VPP is programmed to 5V, D) VPP is disabled.
VCC
Enable
0
A
VCC to 3.3V
t9 t11
5V
VCC 3.3V
OUT
B
C
VCC OFF
t15 t13
VCC to 5V
t10
t12
0
D
VCC OFF
t16
t14
FLAG
0
Figure 2. VCC Timing Diagram
VCC EN is shown generically. RL = 10Ω. Refer to “MIC2568-0 Logic Table” for specific control logic input.
At time A) VCC is programmed to 3.3V, B) VCC is disabled, C) VCC is programmed to 5V, D) VCC is disabled.
May 2003
5
MIC2568
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