MCM63P636 Просмотр технического описания (PDF) - Motorola => Freescale
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MCM63P636 Datasheet PDF : 27 Pages
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PBGA PIN DESCRIPTIONS
Pin Locations
5D
(a) 1B, 2B, 1D, 2D, 3D, 1F, 2F, 1H, 2H,
1K, 2K, 1M, 2M, 1P, 2P, 3P, 1T, 2T
(b) 8B, 9B, 7D, 8D, 9D, 8F, 9F, 8H, 9H,
8K, 9K, 8M, 9M, 7P, 8P, 9P, 8T, 9T
5F
6C
3A, 7A, 3B, 7B, 5M, 5N,
4P, 5P, 6P, 4R, 6R, 3T, 4T, 6T
5R, 5T
4A
5A
4B
5G
3K
3H
7K
7H
5U
3U
7U
4U
6U
5C
4D, 6D, 3E, 7E, 4F, 6F, 3G, 7G,
4H, 6H, 4K, 6K, 3L, 7L, 4M, 6M, 3N, 7N
3F, 7F, 3M, 7M
2A, 8A, 2C, 8C, 2E, 8E, 2G, 8G,
2J, 8J, 2L, 8L, 2N, 8N, 2R, 8R, 2U, 8U
1A, 9A, 1C, 3C, 7C, 9C, 1E, 4E, 5E,
6E, 9E, 1G, 4G, 6G, 9G, 5H, 1J, 3J,
4J, 6J, 7J, 9J, 1L, 4L, 5L, 6L, 9L, 1N,
4N, 6N, 9N, 1R, 3R, 7R, 9R, 1U, 9U
6A, 5B, 5K, 7T
6B
4C, 5J
Symbol
ADS
DQx
Type
Input
I/O
Description
Synchronous Address Status: Active low, used to initiate read or write
state machines latch in external addresses, or deselect chip.
Synchronous Data I/O: “x” refers to the word being read or written
(I/Os a and b).
K
RESET
SA
SA1, SA0
SE1
SE2
SE3
SK
STRBA
STRBA
STRBB
STRBB
TCK
TDI
TDO
TMS
TRST
W
VDD
Input Clock: This signal registers the address, data in, and all control signals.
Input Asynchronous Power–On Reset: Active low at power up, resets internal
state machines.
Input Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
Input
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
Input Synchronous Chip Enable: Active low to enable chip.
Input Synchronous Chip Enable: Active high to enable chip.
Input Synchronous Chip Enable: Active low to enable chip.
Input Data Strobe Clock: 180 degrees out–of–phase with K. Used only with
data strobes.
Output Data Strobe: Used in reference to DQa I/Os.
Output Data Strobe: Used in reference to DQa I/Os.
Output Data Strobe: Used in reference to DQb I/Os.
Output Data Strobe: Used in reference to DQb I/Os.
Input
Input
Boundary Scan Pin, Test Clock: If boundary scan is not used, TCK
must be tied to VDD or VSS.
Boundary Scan Pin, Test Data In.
Output Boundary Scan Pin, Test Data Out.
Input Boundary Scan Pin, Test Mode Select.
Input
Input
Boundary Scan Pin, Asynchronous Test Reset. If boundary scan is not
used, TRST must be tied to VSS.
Synchronous Write.
Supply Core Power Supply.
VDDI
VDDQ
Supply Input Power Supply.
Supply I/O Power Supply.
VSS
Supply Ground.
NC
NU/VDD
NU/VSS
— No Connection: There is no connection to the chip.
— Not Usable: There is an internal connection to the chip. This pin may be
left unconnected or tied to VDD.
— Not Usable: There is an internal connection to the chip. This pin may be
left unconnected or tied to VSS.
MCM63P636
4
MOTOROLA FAST SRAM
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