WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
– 12
– 15
– 20
– 25
Parameter
Symbol Min Max Min Max Min Max Min Max Unit Notes
Write Cycle Time
Address Setup Time
Address Valid to End of Write
Write Pulse Width
tAVAV
12
—
15
—
20
—
25
—
ns
3
tAVWL
0
—
0
—
0
—
0
—
ns
tAVWH 10
—
12
—
15
—
20
—
ns
tWLWH, 10
—
12
—
15
—
20
—
ns
tWLEH
Write Pulse Width,
G High
tWLWH, 10
—
10
—
12
—
15
—
ns
4
tWLEH
Data Valid to End of Write
tDVWH
6
—
7
—
8
—
10
—
ns
Data Hold Time
tWHDX
0
—
0
—
0
—
0
—
ns
Write Low to Output High–Z
tWLQZ —
6
—
7
—
8
—
10
ns 5,6,7
Write High to Output Active
tWHQX
2
—
2
—
2
—
2
—
ns 5,6,7
Write Recovery Time
tWHAX
0
—
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. If G goes low coincident with or after W goes low, the output will remain in a high impedance state.
3. All timings are referenced from the last valid address to the first transitioning address.
4. If G ≥ VIH, the output will remain in a high impedance state.
5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device.
6. Transition is measured ±500 mV from steady–state voltage with load of Figure 1b.
7. This parameter is sampled and not 100% tested.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
tAVAV
tAVWH
tAVWL
HIGH Z
tWLQZ
tWLWH
tWLEH
tDVWH
DATA VALID
HIGH Z
tWHAX
tWHDX
tWHQX
MOTOROLA FAST SRAM
MCM6206BA
5