SSM2161S Просмотр технического описания (PDF) - Analog Devices
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SSM2161S Datasheet PDF : 16 Pages
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SSM2160/SSM2161–SPECIFICATIONS (VS = ؎6 V, TA = +25؇C, AV = 0 dB, fAUDIO = 1 kHz, fCLOCK =
250 kHz, RL = 10 k⍀, unless otherwise noted)
Parameter
Symbol Conditions
Min Typ Max Units
AUDIO PERFORMANCE
Noise floor
Total Harmonic Distortion + Noise
Channel Separation
Dynamic Range
NFL
THD+N
VIN = GND, BW= 20 kHz, AV = 0 dB1
2nd & 3rd Harmonics Only, VOUT = 0 dBu2
AV = 0 dB
Any Channel to Another
NFL to Clip Point
–90
dBu
0.01 0.035 %
80
dB
100
dB
ANALOG INPUT
Maximum Level
Impedance
ANALOG OUTPUT
Maximum Level3
Impedance
Offset Voltage
Minimum Resistive Load
Maximum Capacitive Load
MASTER ATTENUATOR ERROR
AV = 0 dB
AV = –20 dB
AV = –40 dB
AV = –60 dB
CHANNEL MATCHING
VIN max
ZIN
VS = ± 10 V
Any Channel
ZOUT
VS = ± 10 V, All Conditions of Master
Attenuation and Channel Gain
RL min
10
CL max
Measured from Best Fit of All Channels
from 0 dB and –127 dB (or Noise Floor)
Channel Gain = 0 dB
Channel Gain = 0 dB
Channel Gain = 0 dB
Channel Gain = 0 dB
1.8 V rms
10
kΩ
1.8 V rms
10
Ω
20
mV
kΩ
50 pF
± 0.5
dB
± 1.0
dB
± 2.0
dB
± 2.5
dB
± 1.0
dB
CHANNEL GAIN ERROR
AV = 0 dB
AV = +10 dB
AV = +31 dB
Master Attenuation = 0 dB
± 0.5
dB
± 1.0
dB
± 2.0
dB
MUTE ATTENUATION
VIN = 0 dBu
–95
dB
VOLTAGE REFERENCE
Accuracy
Output Impedance
VREF
Percent of (V +) +(V – )
2
±5
%
5
Ω
CONTROL LOGIC
Logic Thresholds
High (1)
Low (0)
Input Current
Clock Frequency
Timing Characteristics
Re: DGND
See Timing Diagrams
2.0
V
0.8 V
±1
µA
1
1000
kHz
POWER SUPPLIES
Voltage Range
SSM2160
SSM2161
SSM2160
SSM2161
Supply Current
VS
V+, V–
Single Supply
Dual Supply
No Load
+10
+8.5
±5
± 4.25
20
+20 V
+20 V
± 10 V
± 10 V
28 mA
NOTES
1Master = 0 dB; Channel = 0 dB.
2Input level adjusted accordingly. 0 dBu = 0.775 V rms.
3For other than ± 10 V supplies, maximum is VS/4.
Specifications subject to change without notice.
–2–
REV. 0
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