NLV74HCT541ADWR2G(2017) Просмотр технического описания (PDF) - ON Semiconductor

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NLV74HCT541ADWR2G
(Rev.:2017)

Octal 3-State Non-Inverting Buffer/Line Driver/Line Receiver With LSTTL-Compatible Inputs

ON Semiconductor 

MC74HCT541A

AC CHARACTERISTICS (VCC = 5.0V, CL = 50 pF, Input tr = tf = 6 ns)

Symbol

Parameter

tPLH,

tPHL

Maximum Propagation Delay, Input A to Output Y

(Figures 1 and 3)

tPLZ,

tPHZ

Maximum Propagation Delay, Output Enable to Output Y

(Figures 2 and 4)

tPZL,

tPZH

Maximum Propagation Delay, Output Enable to Output Y

(Figures 2 and 4)

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

Cin Maximum Input Capacitance

Cout Maximum 3−State Output Capacitance (Output in High Impedance State)

Guaranteed Limit

−55 to 25°C ≤85°C ≤125°C Unit

23

28

32

ns

30

34

38

ns

30

34

38

ns

12

15

18

ns

10

10

10

pF

15

15

15

pF

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Buffer)*

55

pF

* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.

SWITCHING WAVEFORMS

tr

INPUT A

tPLH

90%

1.3V

10%

90%

OUTPUT Y

1.3V

10%

tTLH

Figure 1.

tf

3.0V

GND

tPHL

tTHL

OE1 or OE2

OUTPUT Y

OUTPUT Y

1.3V

tPZL tPLZ

1.3V

tPZH tPHZ

1.3V

1.3V

10%

90%

Figure 2.

3.0V

GND

HIGH

IMPEDANCE

VOL

VOH

HIGH

IMPEDANCE

DEVICE

UNDER

TEST

TEST

POINT

OUTPUT

CL*

TEST CIRCUITS

DEVICE

UNDER

TEST

TEST

POINT

OUTPUT

1kW

CL*

CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.

CONNECT TO GND WHEN

TESTING tPHZ and tPZH.

*Includes all probe and jig capacitance

Figure 3.

*Includes all probe and jig capacitance

Figure 4.

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