SECTION 3
ACTIVATION/DEACTIVATION OF S/T TRANSCEIVER
3.1 INTRODUCTION
CCITT I.430 and ANSI T1.605 define five information states for the S/T transceiver. When the NT
is in the fully operational state it transmits INFO 4. When the TE is in the fully operational state it
transmits INFO 3. INFO 1 is transmitted by the TE when it wants to wake up the NT. INFO 2 is
transmitted by the NT when it wants to wake up the TE, or in response to the TEs transmitted INFO
1. These states cause unique patterns of symbols to be transmitted over the S/T interface. Only
when the S/T loop is in the fully activated state are the 2B+D channels of data transmitted over the
interface.
3.2 TRANSMISSION STATES FOR NT MODE S/T TRANSCEIVER
When configured as an NT, an S/T transceiver can be in any of the following transmission states
shown in Table 3-1.
Table 3-1. NT Mode Transmission States
Information State
INFO 0
INFO 2
INFO 4
Description
The NT transmits 1s in every bit position. This corresponds to no signal
being transmitted.
The NT sets its B1, B2, D, and E channels to ‘0’. The A bit is set to ‘0’ (see
Sections 3.11.1 and 3.11.2).
INFO 4 corresponds to frames containing operational data on the B1, B2,
D, and E channels. The A bit is set to ‘1’.
3.3 TRANSMISSION STATES FOR TE MODE S/T TRANSCEIVER
When configured as a TE, an S/T transceiver can be in any of the following transmission states
shown in Table 3-2.
Table 3-2. TE Mode Transmission States
Information State
INFO 0
INFO 1
INFO 3
Description
The TE transmits 1s in every bit position. This corresponds to no signal
being transmitted.
The TE transmits a continuous signal with the following pattern: positive
zero, negative zero, six ones. This signal is asynchronous to the NT.
INFO 3 corresponds to frames containing operational data on the B1, B2,
and D channels. If INFO 4 or INFO 2 is being received, INFO 3 will be
synchronised to it.
3.4 ACTIVATION OF S/T LOOP BY NT
The NT activates the loop by transmitting INFO 2 to the TE or TEs. This is accomplished in the
MC145474/75 by setting NR2(3) to a ‘1’ (see Section 3.11.3). Note that this bit is internally reset
to ‘0’ after the internal activation state machine has recognized its active transition.
MC145474 • MC145475
MOTOROLA
3-1