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MC145012

Photoelectric Smoke Detector IC with I/O and Temporal Pattern Horn Driver

Freescale Semiconductor 

CALIBRATION

To facilitate checking the sensitivity and calibrating smoke

pin with 100 µA continuously drawn out of the pin for at least

detectors, the MC145012 can be placed in a calibration

one cycle on the OSC pin. To exit this mode, the Test pin is

mode. In this mode, certain device pins are controlled/

floated for at least one OSC cycle.

reconfigured as shown in Table 5. To place the part in the

In the calibration mode, the IRED pulse rate is increased

calibration mode, Pin 16 (Test) must be pulled below the VSS

to one for every OSC cycle. Also, Strobe is always active low.

Table 5. Configuration of Pins in the Calibration Mode

Description

Pin

Comment

I/O

Low-Supply Trip

7

Disabled as an output. Forcing this pin high places the photo amp output on Pin 1 or 2, as determined by Low-

Supply Trip. The amp's output appears as pulses and is referenced to VDD etc.

15 If the I/O pin is high, Pin 15 controls which gain capacitor is used. Low: normal gain, amp output on Pin 1. High:

supervisory gain, amp output on Pin 2.

Feedback

10 Driving this input high enables hysteresis (10% gain increase) in the photo amp; Pin 15 must be low.

OSC

12 Driving this input high brings the internal clock high. Driving the input low brings the internal clock low. If

desired, the RC network for the oscillator may be left intact; this allows the oscillator to run similar to the normal

mode of operation.

Silver

9

This pin becomes the smoke comparator output. When the OSC pin is toggling, positive pulses indicate that

smoke has been detected. A static low level indicates no smoke.

Brass

8

This pin becomes the smoke integrator output. That is, 2 consecutive smoke detections are required for “on”

(static high level) and 2 consecutive no-detections for “off” (static low level).

Do Not Run Any

Additional Traces

In This Region

Pin 16

Pin 1 C1

R14

R11

R8

D2

MOUNTED IN

CHAMBER

Pin 9 PIN 8

NOTES: Illustration is bottom view of layout using a DIP. Top view for SOIC layout is mirror image.

Optional potentiometer R9 is not included.

Drawing is not to scale.

Leads on D2, R11, R8, and R10 and their associated traces must be kept as short as possible. This practice minimizes noise

pick up.

Pin 3 must be decoupled from all other traces.

Figure 9. Recommended PCB Layout

Sensors

Freescale Semiconductor

MC145012

11

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