MC14516B Просмотр технического описания (PDF) - ON Semiconductor

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MC14516B

Binary Up/Down Counter

ON Semiconductor 

PRESET

ENABLE

0 = COUNT

1 = PRESET

1 = UP

0 = DOWN

MC14516B

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q0

Q1

Q2

Q3

PE

Cin

Cout

CLOCK

L.S.D.

MC14516B

U/D

R

P0

P1

P2

P3

Q0

PE

Cin

CLOCK

U/D

R

P0

Q1

Q2

M.S.D.

MC14516B

P1

P2

Q3

Cout

TERMINAL COUNT

INDICATOR

P3

P0

P1

P2

P3

P4

P5

P6

P7

CLOCK

RESET

+VDD

OPEN = COUNT

+VDD

THUMBWHEEL SWITCHES

(OPEN FOR 0")

+VDD

RESISTORS = 10 kW

NOTE: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant

Digit (M.S.D.) is disabled while Cin is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 15 (count

up mode), Cout goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count.

(See Timing Diagram) The L.S.D. now counts through another cycle (15 clock pulses) and the above cycle is repeated.

Figure 3. Presettable Cascaded 8−Bit Up/Down Counter

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