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MC14504B Datasheet PDF : 7 Pages
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MC14504B
Hex Level Shifter for TTL to
CMOS or CMOS to CMOS
The MC14504B is a hex non−inverting level shifter using CMOS
technology. The level shifter will shift a TTL signal to CMOS logic
levels for any CMOS supply voltage between 5 and 15 volts. A control
input also allows interface from CMOS to CMOS at one logic level to
another logic level: Either up or down level translating is
accomplished by selection of power supply levels VDD and VCC. The
VCC level sets the input signal levels while VDD selects the output
voltage levels.
Features
• UP Translates from a Low to a High Voltage or DOWN Translates
from a High to a Low Voltage
• Input Threshold Can Be Shifted for TTL Compatibility
• No Sequencing Required on Power Supplies or Inputs for Power Up
or Power Down
• 3 to 18 Vdc Operation for VDD and VCC
• Diode Protected Inputs to VSS
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VCC DC Supply Voltage Range
VDD DC Supply Voltage Range
Vin
Input Voltage Range
(DC or Transient)
−0.5 to +18.0
V
−0.5 to +18.0
V
−0.5 to +18.0
V
Vout Output Voltage Range
(DC or Transient)
−0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
Tstg Storage Temperature Range
TL
Lead Temperature
(8−Second Soldering)
−55 to +125
°C
−65 to +150
°C
260
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16 16
P SUFFIX
CASE 648
1
MC14504BCP
AWLYYWWG
SOIC−16
D SUFFIX
CASE 751B
16
14504BG
AWLYWW
1
16
TSSOP−16
DT SUFFIX
CASE 948F
14
504B
ALYWG
G
1
SOEIAJ−16
F SUFFIX
CASE 966
16
MC14504B
ALYWG
1
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
1
June, 2011 − Rev. 7
Publication Order Number:
MC14504B/D
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