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MC14012B
(Rev.:2011)

Dual 4-Input NAND Gates

ON Semiconductor 

MC14012B

Dual 4-Input NAND Gates

The MC14012B dual 4−input NAND gates are constructed with

P−Channel and N−Channel enhancement mode devices in a single

monolithic structure (Complementary MOS). Their primary use is

where low power dissipation and/or high noise immunity is desired.

Features

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• All Outputs Buffered

• Capable of Driving Two Low−Power TTL Loads or One Low−Power

Schottky TTL Load Over the Rated Temperature Range

• Double Diode Protection on All Inputs

• Pin−for−Pin Replacements for Corresponding CD4000 Series B

Suffix Devices

• These Devices are Pb−Free and are RoHS Compliant

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol

Parameter

Value

Unit

VDD

Vin, Vout

DC Supply Voltage Range

Input or Output Voltage Range

(DC or Transient)

−0.5 to +18.0

V

−0.5 to VDD + 0.5

V

Iin, Iout

Input or Output Current

(DC or Transient) per Pin

± 10

mA

PD

Power Dissipation, per Package

(Note 1)

500

mW

TA

Ambient Temperature Range

−55 to +125

°C

Tstg

Storage Temperature Range

−65 to +150

°C

TL

Lead Temperature

(8−Second Soldering)

260

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

http://onsemi.com

MARKING

DIAGRAMS

PDIP−14

P SUFFIX

CASE 646

14

MC14012BCP

AWLYYWWG

1

14

SOIC−14

D SUFFIX

CASE 751A

14012BG

AWLYWW

1

A

WL, L

YY, Y

WW, W

G

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

© Semiconductor Components Industries, LLC, 2011

1

June, 2011 − Rev. 9

Publication Order Number:

MC14012B/D

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