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MC10131 Просмотр технического описания (PDF) - ON Semiconductor

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MC10131
ON-Semiconductor
ON Semiconductor ON-Semiconductor
MC10131 Datasheet PDF : 8 Pages
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MC10131
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
–30°C
VIHmax
–0.890
VILmin
–1.890
VIHAmin
–1.205
VILAmax
–1.500
VEE
–5.2
+25°C –0.810 –1.850 –1.105
–1.475
–5.2
+85°C –0.700 –1.825 –1.035
–1.440
–5.2
Characteristic
Power Supply Drain Current
Input Current
Symbol
IE
IinH
Pin
Under
Test
8
4
5
6
7
9
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
VILmin
VIHAmin
VILAmax
4
5
6
7
9
VEE
8
8
8
8
8
8
(VCC)
Gnd
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
IinL
4, 5*
*
6, 7, 9*
*
8
1, 16
8
1, 16
Output Voltage
Logic 1 VOH
2
5
2[
7
8
1, 16
8
1, 16
Output Voltage
Logic 0 VOL
2
5
3[
7
8
1, 16
8
1, 16
Threshold Voltage
Logic 1 VOHA
2
2[
5
8
1, 16
7
9
8
1, 16
Threshold Voltage
Logic 0 VOLA
2
3[
5
8
1, 16
7
9
8
1, 16
Switching Times
Clock Input
(50Load)
+1.11Vdc
Pulse In Pulse Out –3.2 V +2.0 V
Propagation Delay t9+2–
2
t9+2+
2
7
t6+2+
2
7
t6+2–
2
Rise Time
(20 to 80%)
t2+
2
7
Fall Time
(20 to 80%)
t2–
2
9
2
8
1, 16
9
2
8
1, 16
6
2
8
1, 16
6
2
8
1, 16
9
2
8
1, 16
9
2
8
1, 16
Set Input
Propagation Delay t5+2+
2
t12+15+
15
6
t5+3–
3
t12+14–
14
9
5
2
8
1, 16
12
15
8
1, 16
5
3
8
1, 16
12
14
8
1, 16
Reset Input
Propagation Delay t4+2–
2
t13+15–
15
6
t4+3–
3
t13+14+
14
9
4
2
8
1, 16
13
15
8
1, 16
4
3
8
1, 16
13
14
8
1, 16
Setup Time
tsetup
7
6, 7
2
8
1, 16
Hold Time
thold
7
6, 7
2
8
1, 16
Toggle Frequency (Max)
ftog
2
6
2
8
1, 16
* Individually test each input applying VIH or VIL to input under test.
[ Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)
VIHmax
VILmin
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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