MB86626 Просмотр технического описания (PDF) - Fujitsu

Номер в каталоге

Компоненты Описание

Список матч

MB86626

KeyWave™ AFE ADSL Analog Front End

Fujitsu 

January 2002 Version 1.2

FME/MS/ADSLAFE/FL_1/4282

MB86626 KeyWave™AFE ADSL Analog Front End

Functional Description

The analog circuitry consists of two 15-bit DACs with associated anti-imaging filters, two 15-bit ADCs

with anti-aliasing filters and two programmable gain summing amplifiers (PGA). A clock multiplier and

bandgap reference are incorporated on-chip. A configurable data interface allows for high speed data

transfer of the receive/transmit data, while a serial interface is provided for control and configuration.

All analog signal paths are differential. This highly integrated device reduces the number of

components required for the line interface to a transmit line driver and a small number of passive

components. Analog echo cancellation at the RT attenuates the transmit echo at the input of the PGA

allowing higher gain before the ADC. This gives lower receiver noise on long lines. A functional block

diagram is shown in Figure 1.

The device is manufactured in a 0.35µm CMOS process with Triple Well extension giving improved

isolation between analog blocks and digital-analog.

R/W*

Sync.

Clk. In

VCXO

15

DAC

15

DAC

16

15

ADC

15

ADC

PA Control

PA Control

PGA

Σ

PGA

Tx1

PAC1

Tx2

PAC2

Rx1

Trim

Rx2

Clock

Generator

VCXO Control

Serial

Control I/F

4

Voltage

Reference

Rx Test P

Rx Test M

Ext. Ref.

Serial Control

Figure 1 KeyWave™AFE Functional Block Diagram

Page 2 of 6

Copyright © 2002 Fujitsu Microelectronics Europe GmbH

Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before

ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.

Share Link: