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MAX7480ESA

8th-Order, Lowpass, Butterworth, Switched-Capacitor Filter

Maxim Integrated 

8th-Order, Lowpass, Butterworth,

Switched-Capacitor Filter

Clock Signal

External Clock

The MAX7480 SCF is designed for use with external

clocks that have a 40% to 60% duty cycle. When using

an external clock with these devices, drive CLK with a

CMOS gate powered from 0 to VDD. Varying the rate of

the external clock adjusts the corner frequency of the

filter as follows:

fC = fCLK / 100

Internal Clock

When using the internal oscillator, connect a capacitor

(COSC) between CLK and ground. The value of the

capacitor determines the oscillator frequency as follows:

fOSC(kHz) =

53 ⋅103

COSC

;

C OSC

in

pF

Minimize the stray capacitance at CLK so that it does

not affect the internal oscillator frequency. Vary the rate

of the internal oscillator to adjust the filter’s corner fre-

quency by a 100:1 clock to corner-frequency ratio. For

example, an internal oscillator frequency of 100kHz

produces a nominal corner frequency of 1kHz.

Input Impedance vs. Clock Frequencies

The MAX7480’s input impedance is effectively that of a

switched-capacitor resistor, and is inversely proportion-

al to frequency. The input impedance values deter-

mined below represent the average input impedance,

since the input current is not continuous. As a rule, use

a driver with an output impedance less than 10% of the

filter’s input impedance. Estimate the input impedance

of the filter using the following formula:

( ) ZIN =

1

fCLK ⋅ CIN

where fCLK = clock frequency and CIN = 2.31pF.

Low-Power Shutdown Mode

This device features a shutdown mode that is activated

by driving SHDN low. In shutdown mode, the filter’s sup-

ply current reduces to 0.2µA (typ) and its output

becomes high impedance. For normal operation, drive

SHDN high or connect to VDD.

___________Applications Information

Offset and Common-Mode

Input Adjustment

The voltage at COM sets the common-mode input volt-

age and is biased at mid-supply with an internal resis-

tor-divider. Bypass COM with a 0.1µF capacitor and

connect OS to COM. For applications requiring offset

adjustment or DC level shifting, apply an external bias

voltage through a resistor-divider network to OS, as

shown in Figure 3. (Note: Do not leave OS unconnect-

ed.) The output voltage is represented by this equation:

VOUT = (VIN - VCOM) + VOS

with VCOM = VDD / 2 (typical), where (VIN - VCOM) is

lowpass-filtered by the SCF and VOS is added at the

output stage. See the Electrical Characteristics for the

voltage range of COM and OS. Changing the voltage

on COM or OS significantly from mid-supply reduces

the filter’s dynamic range.

Power Supplies

The MAX7480 operates from a single +5V supply.

Bypass VDD to GND with a 0.1µF capacitor. If dual

supplies (±2.5V) are required, connect COM to system

ground and connect GND to the negative supply.

Figure 4 shows an example of dual-supply operation.

Single- and dual-supply performances are equivalent.

For either single- or dual-supply operation, drive CLK

and SHDN from GND (V- in dual-supply operation) to

VDD. For ±5V dual-supply applications, use the

MAX291–MAX297.

Input Signal Amplitude Range

The optimal input signal range is determined by observ-

ing the voltage level at which the total harmonic distor-

tion plus noise (THD+N) is minimized for a given corner

frequency. The Typical Operating Characteristics

shows a graph of the device’s THD+N response as the

input signal’s peak-to-peak amplitude is varied. This

measurement is made with OS and COM biased at mid-

supply.

VSUPPLY

0.1µF

VDD

SHDN

OUT OUTPUT

INPUT IN

COM

0.1µF

50k

MAX7480

CLOCK CLK

OS

50k

0.1µF

50k

GND

Figure 3. Offset Adjustment Circuit

_______________________________________________________________________________________ 7

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