MAX5811 Просмотр технического описания (PDF) - Maxim Integrated

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MAX5811

10-Bit, Low-Power, 2-Wire Interface, Serial, Voltage-Output DAC

Maxim Integrated 

10-Bit Low Power 2-Wire Interface Serial,

Voltage-Output DAC

SDA

SCL

tHD, STA

tSU, DAT

tLOW

tHIGH

tHD, DAT

tR

tF

tSU, STA

tHD, STA

tBUF

tSP

tSU, STO

START CONDITION

REPEATED START CONDITION

STOP

CONDITION

Figure 1. 2-Wire Serial lnterface Timing Diagram

a serial clock line (SCL). The MAX5811 is SMBus com-

S

Sr

patible within the range of VDD = 2.7V to 3.6V. SDA and

SCL

SCL facilitate bidirectional communication between the

MAX5811 and the master at rates up to 400kHz. Figure

1 shows the 2-wire interface timing diagram. The

MAX5811 is a transmit/receive slave-only device, rely-

SDA

ing upon a master to generate a clock signal. The mas-

ter (typically a microcontroller) initiates data transfer on

the bus and generates SCL to permit that transfer.

A master device communicates to the MAX5811 by

transmitting the proper address followed by command

and/or data words. Each transmit sequence is framed

by a START (S) or REPEATED START (Sr) condition and

a STOP (P) condition. Each word transmitted over the

bus is 8 bits long and is always followed by an

acknowledge clock pulse.

Figure 2. START/STOP Conditions

SCL

SDA

The MAX5811 SDA and SCL drivers are open-drain

outputs, requiring a pullup resistor (500Ω or greater) to

generate a logic high voltage (see Typical Operating

STOP

START

LEGAL STOP CONDITION

Circuit). Series resistors RS are optional. These series

resistors protect the input stages of the MAX5811 from

SCL

high-voltage spikes on the bus lines, and minimize

crosstalk and undershoot of the bus signals.

SDA

START

CONDITION

P

Bit Transfer

One data bit is transferred during each SCL clock

cycle. The data on SDA must remain stable during the

high period of the SCL clock pulse. Changes in SDA

while SCL is high are control signals (see START and

STOP Conditions). SDA and SCL idle high when the

I2C bus is not busy.

START

ILLEGAL

STOP

ILLEGAL EARLY STOP CONDITION

Figure 3. Early STOP Condition

START and STOP Conditions

When the serial interface is inactive, SDA and SCL idle

high. A master device initiates communication by issu-

ing a START condition. A START condition is a high-to-

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