MAX5811 Просмотр технического описания (PDF) - Maxim Integrated

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MAX5811

10-Bit, Low-Power, 2-Wire Interface, Serial, Voltage-Output DAC

Maxim Integrated 

10-Bit Low Power 2-Wire Interface Serial,

Voltage-Output DAC

ELECTRICAL CHARACTERISTICS (continued)

(VDD = +2.7V to +5.5V, GND = 0, RL = 5kΩ, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at

VDD = +5V, TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

DYNAMIC PERFORMANCE

Voltage-Output Slew Rate

SR

Voltage-Output Settling Time

To 1/2LSB code 100 hex to 300 hex or 300

hex to 100 hex (Note 5)

Digital Feedthrough

Code = 000 hex, digital inputs from 0 to VDD

Digital-to-Analog Glitch Impulse

Major-carry transition (code = 1FF hex to 200

hex and 200 hex to 1FF hex)

POWER SUPPLIES

Supply Voltage Range

VDD

2.7

Supply Current with

All digital inputs at 0 or VDD = 3.6V

No Load

All digital inputs at 0 or VDD = 5.5V

Power-Down Supply Current

All digital inputs at 0 or VDD = 5.5V

TIMING CHARACTERISTICS (Figure 1)

Serial Clock Frequency

fSCL

0

Bus-Free Time Between STOP

and START Conditions

tBUF

1.3

START Condition Hold Time

tHD,STA

0.6

SCL Pulse Width Low

tLOW

1.3

SCL Pulse Width High

tHIGH

0.6

Repeated START Setup Time

tSU,STA

0.6

Data Hold Time

tHD,DAT

0

Data Setup Time

tSU,DAT

100

SDA and SCL Receiving

Rise Time

tr

(Note 5)

0

TYP MAX UNITS

0.5

V/µs

4

12

µs

0.2

nV-s

12

nV-s

5.5

V

100

170

130

190

0.3

1

µA

400 kHz

µs

µs

µs

µs

µs

0.9

µs

ns

300

ns

SDA and SCL Receiving

Fall Time

tf

(Note 5)

0

300

ns

SDA Transmitting Fall Time

STOP Condition Setup Time

Bus Capacitance

Maximum Duration of

Suppressed Pulse Widths

tf

(Note 5)

tSU,STO

Cb (Note 5)

tSP

20 +

0.1Cb

0.6

0

250

ns

µs

400

pF

50

ns

Note 1: All devices are 100% production tested at TA = +25°C and are guaranteed by design for TA = TMIN to TMAX.

Note 2: Static specifications are tested with the output unloaded.

Note 3: Linearity is guaranteed from codes 29 to 995.

Note 4: Offset and gain error limit the FSR.

Note 5: Guaranteed by design. Not production tested.

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