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MAX4678EPE

2Ω, Quad, SPST, CMOS Analog Switches

Maxim Integrated 

2Ω, Quad, SPST, CMOS Analog Switches

___________Applications Information

Overvoltage Protection

Proper power-supply sequencing is recommended for

all CMOS devices. Do not exceed the absolute maxi-

mum ratings because stresses beyond the listed ratings

can cause permanent damage to the devices. Always

sequence V+ on first, then V-, then VL followed by the

logic inputs, NO_, NC_, or COM. If proper power-supply

sequencing is not possible, add two small signal diodes

(D1, D2) in series with the supply pins, and a Schottky

diode between V+ and VL for overvoltage protection

(Figure 1). Adding diodes reduces the analog signal

range to one diode drop below V+ and one diode drop

above V-, but does not affect the devices’ low switch

resistance and low leakage characteristics. Device oper-

ation is unchanged, and the difference between V+ and

V- should not exceed 11V.

Power-supply bypassing improves noise margin and

prevents switching noise from propagating from the V+

supply to other components. A 0.1µF capacitor connect-

ed from V+ to GND is adequate for most applications.

MAX4677

MAX4678

MAX4679

V+

D1

*

COM_

V2

*

*

VL

NO_

*

D2

V-

*INTERNAL PROTECTION DIODES

Figure 1. Overvoltage Protection Using External Blocking Diodes

MAX4677

MAX4678

MAX4679

SWITCH

INPUT

VCOM

V+

VL

COM_

V+

V+

NO_

OR NC_

IN_

LOGIC

INPUT

GND

V-

0V

V-

SWITCH

OUTPUT

VOUT

RL

CL

300Ω

35pF

CL INCLUDES FIXTURE AND STRAY CAPACITANCE.

( ) VOUT = VCOM

RL

RL + RON

Figure 2. Switching Time

+3V

LOGIC

INPUT 0

SWITCH 0

OUTPUT

tr < 20ns

tf < 20ns

50%

tOFF

VOUT 0.9 x V0UT

tON

0.9 x VOUT

MAX4679

VCOM1 = +3V

VCOM2 = +3V

V+

COM1 VL

COM2

V+

V+

NO1

NC2

VOUT2 RL1

LOGIC

INPUT

IN1

RL2

CL2

IN2

GND

V-

V-

RL = 300Ω

CL INCLUDES FIXTURE AND STRAY CAPACITANCE. CL = 35pF

Figure 3. Break-Before-Make Interval (MAX4679 Only)

VOUT1

CL1

LOGIC +3V

INPUT

0

SWITCH

OUTPUT 1

(VOUT1)

0

SWITCH

OUTPUT 2

(VOUT2)

0

50%

0.9 x V0UT1

tD

tD

8 _______________________________________________________________________________________

0.9 x VOUT2

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