MAX147ACAP Просмотр технического описания (PDF) - Maxim Integrated

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MAX147ACAP

+2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs

Maxim Integrated 

+2.7V, Low-Power, 8-Channel,

Serial 12-Bit ADCs

How to Start a Conversion

Start a conversion by clocking a control byte into DIN.

With CS low, each rising edge on SCLK clocks a bit from

DIN into the MAX146/MAX147’s internal shift register.

After CS falls, the first arriving logic “1” bit defines the

control byte’s MSB. Until this first “start” bit arrives, any

number of logic “0” bits can be clocked into DIN with no

effect. Table 1 shows the control-byte format.

The MAX146/MAX147 are compatible with SPI™/

QSPI™ and Microwire™ devices. For SPI, select the

correct clock polarity and sampling edge in the SPI

control registers: set CPOL = 0 and CPHA = 0. Micro-

wire, SPI, and QSPI all transmit a byte and receive a

byte at the same time. Using the Typical Operating

Circuit, the simplest software interface requires only

three 8-bit transfers to perform a conversion (one 8-bit

transfer to configure the ADC, and two more 8-bit trans-

fers to clock out the 12-bit conversion result). See Figure

20 for MAX146/MAX147 QSPI connections.

Simple Software Interface

Make sure the CPU’s serial interface runs in master

mode so the CPU generates the serial clock. Choose a

clock frequency from 100kHz to 2MHz.

1) Set up the control byte for external clock mode and

call it TB1. TB1 should be of the format: 1XXXXX11

binary, where the Xs denote the particular channel

and conversion mode selected.

2) Use a general-purpose I/O line on the CPU to pull

CS low.

3) Transmit TB1 and, simultaneously, receive a byte

and call it RB1. Ignore RB1.

4) Transmit a byte of all zeros ($00 hex) and, simulta-

neously, receive byte RB2.

5) Transmit a byte of all zeros ($00 hex) and, simulta-

neously, receive byte RB3.

6) Pull CS high.

Figure 6 shows the timing for this sequence. Bytes RB2

and RB3 contain the result of the conversion, padded

with one leading zero and three trailing zeros. The total

conversion time is a function of the serial-clock fre-

quency and the amount of idle time between 8-bit

transfers. To avoid excessive T/H droop, make sure the

total conversion time does not exceed 120µs.

Digital Output

In unipolar input mode, the output is straight binary

(Figure 17). For bipolar input mode, the output is two’s

complement (Figure 18). Data is clocked out at the

falling edge of SCLK in MSB-first format.

Clock Modes

The MAX146/MAX147 may use either an external

serial clock or the internal clock to perform the succes-

sive-approximation conversion. In both clock modes,

the external clock shifts data in and out of the

MAX146/MAX147. The T/H acquires the input signal as

the last three bits of the control byte are clocked into

DIN. Bits PD1 and PD0 of the control byte program the

clock mode. Figures 7–10 show the timing characteris-

tics common to both modes.

CS

SCLK

1

tACQ

4

8

DIN

SSTRB

DOUT

SEL2 SEL1 SEL0

UNI/

BIP

SGL/

DIF

PD1

PD0

START

RB1

A/D STATE

ACQUISITION

IDLE

1.5µs

(fSCLK = 2MHz)

12

16

20

24

RB2

RB3

B11

MSB

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

LSB

FILLED WITH

ZEROS

CONVERSION

IDLE

Figure 6. 24-Clock External Clock Mode Conversion Timing (Microwire and SPI Compatible, QSPI Compatible with fSCLK ≤ 2MHz)

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