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MAX1204ACAP(2012) Просмотр технического описания (PDF) - Maxim Integrated

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Список матч
MAX1204ACAP
(Rev.:2012)
MaximIC
Maxim Integrated MaximIC
MAX1204ACAP Datasheet PDF : 23 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
ELECTRICAL CHARACTERISTICS (continued)
VDD = +5V ±5%, VL = 2.7V to 3.6V; VSS = 0V or -5V ±5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); 4.7µF capacitor at REF; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
SYMBOL
EXTERNAL REFERENCE AT REFADJ
Capacitive Bypass at REF
Reference-Buffer Gain
REFADJ Input Current
POWER REQUIREMENTS
Positive Supply Voltage
VDD
Negative Supply Voltage
VSS
Positive Supply Current
IDD
Negative Supply Current
ISS
Logic Supply Voltage
VL
Logic Supply Current (Notes 6, 10) IVL
Positive Supply Rejection
(Note 11)
PSR
CONDITIONS
Internal compensation mode
External compensation mode
Operating mode
Fast power-down (Note 9)
Full power-down (Note 9)
Operating mode and fast power-down
Full power-down
VL = VDD = 5V
VDD = 5V ±5%; external reference, 4.096V;
full-scale input
MIN TYP MAX UNITS
0
µF
4.7
1.68
V/V
±50
µA
µA
5 ±5%
V
0 or -5 ±5%
V
1.5
2.5
mA
30
70
µA
2
10
50
µA
10
2.70
5.25
V
10
µA
±0.06 ±0.5 mV
Negative Supply Rejection
(Note 11)
PSR
VSS = -5V ±5%; external reference, 4.096V;
full-scale input
±0.01 ±0.5 mV
Logic Supply Rejection
(Note 12)
PSR External reference, 4.096V; full-scale input
±0.06 ±0.5 mV
4
Maxim Integrated

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