MAX115 Просмотр технического описания (PDF) - Maxim Integrated
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MAX115 Datasheet PDF : 14 Pages
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2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = +5V ±5%, AVSS = -5V ±5%, DVDD = +5V ±5%, VREFIN = +2.5V (external reference), AGND = DGND = 0, 4.7µF capacitor
from REFOUT to AGND, 0.1µF capacitor from REFIN to AGND, fCLK = 16MHz, external clock, 50% duty cycle. TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
DIGITAL OUTPUTS (D0–D11, INT)
Output High Voltage
VOH
Output Low Voltage
VOL
Three-State Leakage Current
CONDITIONS
IOUT = 1mA
IOUT = -1.6mA
D0–D11
MIN TYP MAX UNITS
4
V
0.4
V
±10
µA
Three-State Output
Capacitance
10
pF
POWER REQUIREMENTS
Positive Supply Voltage
Negative Supply Voltage
Digital Supply Voltage
Positive Supply Current
Negative Supply Current
Digital Supply Current
Shutdown Positive Current
AVDD
AVSS
DVDD
IAVDD
IAVSS
4.75
5
5.25
V
-5.25
-5
-4.75
V
4.75
5
5.25
V
17
25
mA
-20
-15
mA
3
6
mA
1
µA
Shutdown Negative Current
Shutdown Digital Current
Positive Supply Rejection
Negative Supply Rejection
Power Dissipation
PSRR+
PSRR-
(Note 10)
(Note 10)
(Note 11)
-1
µA
13
µA
±1
LSB
±1
LSB
175
mW
TIMING CHARACTERISTICS
(See Figure 4, AVDD = +5V, AVSS = -5V, DVDD = +5V, AGND = DGND = 0, TA = TMIN to TMAX, Typical values are at TA = +25°C,
unless otherwise noted.)
PARAMETER
CONVST Pulse Width
CS to WR Setup Time
CS to WR Hold Time
WR Low Pulse Width
Address Setup Time
Address Hold Time
RD to INT Delay
Delay Time Between Reads
CS to RD Setup Time
CS to RD Hold Time
RD Low Pulse Width
SYMBOL
tCW
tCWS
tCWH
tWR
tAS
tAH
tID
tRD
tCRS
tCRH
tRD
CONDITIONS
Guaranteed by design
Guaranteed by design
25pF load
Guaranteed by design
Guaranteed by design
MIN TYP MAX UNITS
30
ns
0
ns
0
ns
30
ns
30
ns
0
ns
55
ns
45
ns
0
ns
0
ns
30
ns
Data-Access Time
Bus-Relinquish Time
tDA
25pF load (Note 12)
tDH 25pF load (Note 13)
40
ns
5
45
ns
4 _______________________________________________________________________________________
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