CY7C43686-15AC Просмотр технического описания (PDF) - Cypress Semiconductor
Номер в каталоге
Компоненты Описание
Список матч
CY7C43686-15AC Datasheet PDF : 39 Pages
| |||
CY7C43646
CY7C43666
CY7C43686
the most significant byte (word) of the long-word written to Port
A will be transferred to Port B last. When data is moving in the
direction from Port C to Port A, the byte (word) written to Port
C first will be transferred to port A as the least significant byte
(word) of the long-word; the byte (word) written to Port C last
will be transferred to Port A as the most significant byte (word)
of the long- word.
After Master Reset, the FWFT select function is active,
permitting a choice between two possible timing modes: CY
Standard Mode or First-Word Fall-Through (FWFT) Mode.
Once the Master Reset (MRS1, MRS2) input is HIGH, a HIGH
on the BE/FWFT input during the next LOW-to-HIGH transition
of CLKA (for FIFO1) and CLKB (for FIFO2) will select CY
Standard Mode. This mode uses the Empty Flag function
(EFA, EFB) to indicate whether or not there are any words
present in the FIFO memory. It uses the Full Flag function
(FFA, FFC) to indicate whether or not the FIFO memory has
any free space for writing. In CY Standard Mode, every word
read from the FIFO, including the first, must be requested
using a formal read operation.
Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW
on the BE/FWFT input at the second LOW-to-HIGH transition
of CLKA (for FIFO1) and CLKC (for FIFO2) will select FWFT
Mode. This mode uses the Output Ready function (ORA,
ORB) to indicate whether or not there is valid data at the data
outputs (A0–35 or B0–17). It also uses the Input Ready function
(IRA, IRC) to indicate whether or not the FIFO memory has
any free space for writing. In the FWFT mode, the first word
written to an empty FIFO goes directly to data outputs, no read
request necessary. Subsequent words must be accessed by
performing a formal read operation.
Following Master Reset, the level applied to the BE/FWFT
input to choose the desired timing mode must remain static
throughout the FIFO operation.
Programming the Almost Empty and Almost Full Flags
Four registers in the CY7C436X6 are used to hold the offset
values for the Almost Empty and Almost Full flags. The Port B
Almost Empty flag (AEB) offset register is labeled X1 and the
Port A Almost Empty flag (AEA) offset register is labeled X2.
The Port A Almost Full flag (AFA) offset register is labeled Y1
and the Port C Almost Full flag (AFC) offset register is labeled
Y2. The index of each register name corresponds with preset
values during the reset of a FIFO, programmed in parallel
using the FIFO’s Port A data inputs, or programmed in serial
using the Serial Data (SD) input (see Table 1).
To load a FIFO’s Almost Empty flag and Almost Full flag offset
registers with one of the three preset values listed in Table 1.
The Serial Program Mode (SPM) and at least one of the
flag-select inputs must be HIGH during the LOW-to-HIGH
transition of its Master Reset input (MRS1 and MRS2). For
example, to load the preset value of 64 into X1 and Y1, SPM,
FS0, and FS1 must be HIGH when FIFO1 reset (MRS1)
returns HIGH. Flag-offset registers associated with FIFO2 are
loaded with one of the preset values in the same way with
Master Reset (MRS2). When using one of the preset values
for the flag offsets, the FIFOs can be reset simultaneously or
at different times.
To program the X1, X2, Y1, and Y2 registers from Port A,
perform a Master Reset on both FIFOs simultaneously with
SPM HIGH and FS0 and FS1 LOW during the LOW-to-HIGH
transition of MRS1 and MRS2. After this reset is complete, the
first four writes to FIFO1 do not store data in RAM but load the
offset registers in the order Y1, X1, Y2, X2. The Port A data
inputs used by the offset registers are (A0–9), (A0–11), or
(A0–13), for the CY7C436X6, respectively. The highest
numbered input is used as the most significant bit of the binary
number in each case. Valid programming values for the
registers range from 0 to 1023 for the CY7C43646; 1 to 4095
for the CY7C43666; 0to 16383 for the CY7C43686. After all
the offset registers are programmed from Port A, the Port C
Full/Input Ready (FFC/IRC) is set HIGH and both FIFOs begin
normal operation.
To program the X1, X2, Y1, and Y2 registers serially, initiate a
Master Reset with SPM LOW, FS0/SD LOW and FS1/SEN
HIGH during the LOW-to-HIGH transition of MRS1 and MRS2.
After this reset is complete, the X and Y register values are
loaded bit-wise through the FS0/SD input on each
LOW-to-HIGH transition of CLKA that the FS1/SEN input is
LOW. 40, 48, or 56 bit writes are needed to complete the
programming for the CY7C436X6, respectively. The four
registers are written in the order Y1, X1, Y2, and, finally, X2.
The first-bit write stores the most significant bit of the Y1
register and the last-bit write stores the least significant bit of
the X2 register. Each register value can be programmed from
0 to 1023 (CY7C43646), 0 to 4095 (CY7C43666), or 0 to
16383 (CY7C43686).
When the option to program the offset registers serially is
chosen, the Port A Full/Input Ready (FFA/IRA) flag remains
LOW until all register bits are written. FFA/IRA is set HIGH by
the LOW-to-HIGH transition of CLKA after the last bit is loaded
to allow normal FIFO1 operation. The Port C Full/Input ready
(FFC/IRC) flag also remains LOW throughout the serial
programming process, until all register bits are written.
FFC/IRC is set HIGH by the LOW-to-HIGH transition of CLKC
after the last bit is loaded to allow normal FIFO2 operation.
SPM, FS0/SD, and FS1/SEN function the same way in both
CY Standard and FWFT modes.
FIFO Write/Read Operation
The state of the Port A data (A0–35) lines is controlled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A0–35 lines are in the high-impedance state when either
CSA or W/RA is HIGH. The A0–35 lines are active outputs
when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0–35 inputs on a
LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is
HIGH, ENA is HIGH, MBA is LOW, and FFA/IRA is HIGH. Data
is read from FIFO2 to the A0–35 outputs by a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is LOW, ENA is
HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2).
FIFO reads and writes on Port A are independent of any
concurrent Port B operation.
The state of the Port B data (B0–17) lines is controlled by the
Port B Chip Select (CSB) and Port B Read select (RENB). The
B0–17 lines are in the high-impedance state when either CSB
is HIGH or RENB is LOW. The B0–17 lines are active outputs
when CSB is LOW and RENB is HIGH.
Data is loaded into FIFO2 from the C0–17 inputs on a
LOW-to-HIGH transition of CLKC when WENC is LOW, MBC
is LOW, and FFC/IRC is HIGH. Data is read from FIFO1 to the
B0–17 outputs by a LOW-to-HIGH transition of CLKB when
CSB is LOW, RENB is HIGH, MBB is LOW, and EFB/ORB is
Document #: 38-06023 Rev. *C
Page 7 of 39
Share Link: 