CY7C43686-7AC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C43686-7AC Datasheet PDF : 39 Pages
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CY7C43646
CY7C43666
CY7C43686
Functional Description
The CY7C436X6 is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous (clocked) FIFO memory,
which supports clock frequencies up to 133 MHz and has read
access times as fast as 6 ns. Two independent 1K/4K/16K x36
dual-port SRAM FIFOs on board each chip buffer data in
opposite directions.
The CY7C436X6 is a synchronous (clocked) FIFO, meaning
each port employs a synchronous interface. All data transfers
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide
a simple bidirectional interface between microprocessors
and/or buses with synchronous control.
Communication between each port may bypass the FIFOs via
two mailbox registers. The mailbox registers’ width matches
the selected Port B or Port C bus width. Each mailbox register
has a flag (MBF1 and MBF2) to signal when new mail has
been stored.
Two kinds of reset are available on the CY7C436X6: Master
Reset and Partial Reset. Master Reset initializes the read and
write pointers to the first location of the memory array,
configures the FIFO for Big or Little Endian byte arrangement
and selects serial flag programming, parallel flag
programming, or one of the three possible default flag offset
settings, 8, 16, or 64. Each FIFO has its own independent
Master Reset pin, MRS1 and MRS2.
Partial Reset also sets the read and write pointers to the first
location of the memory. Unlike Master Reset, any settings
existing prior to Partial Reset (i.e., programming method and
partial flag default offsets) are retained. Partial Reset is useful
since it permits flushing of the FIFO memory without changing
any configuration settings. Each FIFO has its own,
independent Partial Reset pin, PRS1 and PRS2.
The CY7C436X6 have two modes of operation. In the CY
Standard Mode, the first word written to an empty FIFO is
deposited into the memory array. A read operation is required
to access that word (along with all other words residing in
memory). In the First-Word Fall-Through Mode (FWFT), the
first long-word (36-bit-wide) written to an empty FIFO appears
automatically on the outputs, no read operation required
(nevertheless, accessing subsequent words does necessitate
a formal read request). The state of the BE/FWFT pin during
FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready flag
(EFA/ORA and EFB/ORB) and a combined Full/Input Ready
flag (FFA/IRA and FFC/IRC). The EF and FF functions are
selected in the CY Standard Mode. EF indicates whether the
memory is full or not. The IR and OR functions are selected in
the First-Word Fall-Through Mode. IR indicates whether or not
the FIFO has available memory locations. OR shows whether
the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.[1]
Each FIFO has a programmable Almost Empty flag (AEA and
AEB) and a programmable Almost Full flag (AFA and AFC).
AEA and AEB indicate when a selected number of words
written to FIFO memory achieve a predetermined “almost
empty state.” AFA and AFC indicate when a selected number
of words written to the memory achieve a predetermined
“almost full state.”[2]
IRA, IRC, AFA, and AFC are synchronized to the port clock
that writes data into its array. ORA, ORB, AEA, and AEB are
synchronized to the port clock that reads data from its array.
Programmable offset for AEA, AEB, AFA, and AFC are loaded
in parallel using Port A or in serial via the SD input. Three
default offset settings are also provided. The AEA and AEB
threshold can be set at 8, 16, or 64 locations from the empty
boundary and AFA and AFC threshold can be set at 8, 16, or
64 locations from the full boundary. All these choices are made
using the FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths. Such a width expansion requires no additional
external components.
The CY7C436X6 are characterized for operation from 0°C to
70°C commercial, and from –40°C to 85°C industrial. Input
ESD protection is greater than 2001V, and latch-up is prevented by
the use of guard rings.
Pin Definitions
Signal Name Description
A0–35
AEA
Port A Data
Port A Almost
Empty Flag
AEB
Port B Almost
Empty Flag
AFA
Port A Almost
Full Flag
AFC
Port C Almost
Full Flag
B0–17
Port B Data
I/O
Function
I/O 36-bit bidirectional data port for side A.
O Programmable Almost Empty flag synchronized to CLKA. It is LOW when the
number of words in FIFO2 is less than or equal to the value in the Almost Empty A
offset register, X2.[2]
O Programmable Almost Empty flag synchronized to CLKB. It is LOW when the
number of words in FIFO1 is less than or equal to the value in the Almost Empty B
offset register, X1.[2]
O Programmable Almost Full flag synchronized to CLKA. It is LOW when the number
of empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset
register, Y1.[2]
O Programmable Almost Full flag synchronized to CLKC. It is LOW when the number
of empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset
register, Y2.[2]
O 18-bit output data port for port B.
Document #: 38-06023 Rev. *C
Page 3 of 39
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