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M95040-SBN3T Просмотр технического описания (PDF) - STMicroelectronics

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M95040-SBN3T Datasheet PDF : 33 Pages
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M95040, M95020, M95010
SUMMARY DESCRIPTION
The M95040 is a 4 Kbit (512 x 8) electrically eras-
able programmable memory (EEPROM), access-
ed by a high speed SPI-compatible bus. The other
members of the family (M95020, M95010) are
identical, though proportionally smaller (2 and 1
Kbit, respectively).
Each device is accessed by a simple serial
interface that is SPI-compatible. The bus signals
are C, D and Q, as shown in Table 1 and Figure 2.
The device is selected when Chip Select (S) is tak-
en Low. Communications with the device can be
interrupted using Hold (HOLD). WRITE instruc-
tions are disabled by Write Protect (W).
Figure 2. Logic Diagram
VCC
Figure 3. DIP, SO and TSSOP Connections
M95xxx
S1
Q2
8 VCC
7 HOLD
W3
6C
VSS 4
5D
AI01790D
Note: 1. See page 28 (onwards) for package dimensions, and how
to identify pin-1.
D
C
S
W
HOLD
M95xxx
VSS
Q
AI01789C
Table 1. Signal Names
C
Serial Clock
D
Serial Data Input
Q
Serial Data Output
S
Chip Select
W
Write Protect
HOLD
Hold
VCC
Supply Voltage
VSS
Ground
2/33

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