MP7680
CS
A0, A1
B1/B2
DATA
WR1
XFER
WR2
tCS
tAS
VALID
tBS
tDS
VALID
tWR
tH
tH
tBH
tDH
tWC
NOTES:
1. t XFER is the timing of the condition XFER = WR2
= Low .
2. The timing of Figure 2. reproduces graphically
the conditions that all control signals must meet
in any of the many possible writing cycles (see
Theory of Operation).
tXFER
Figure 2. W rite Cycle T iming (Each DAC)
Rev. 3.10
7