AS7C1026A-JC Просмотр технического описания (PDF) - Alliance Semiconductor
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AS7C1026A-JC Datasheet PDF : 9 Pages
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AS7C1026A
AS7C31026A
®
Functional description
The AS7C1026A and AS7C31026A are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as
65,536 words × 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 3/3/4/5 ns are ideal for
high-performance applications.
When CE is high the devices enter standby mode. The AS7C1026A is guaranteed not to exceed 55 mW power consumption in CMOS
standby mode. The devices also offer 2.0V data retention.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0–I/O15 is written on the
rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs
have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. the chips drive I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output
drivers stay in high-impedance mode.
The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1026A) or 3.3V supply (AS7C31026A). the
device is packaged in common industry standard packages. Chip scale BGA packaging, easy to use in manufacturing, provides the smallest
possible footprint. This 48-ball JEDEC-registered package has a ball pitch of 0.75 mm and external dimensions of 8 mm × 6 mm.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Voltage on VCC relative to GND
AS7C1026A
Vt1
AS7C31026A
Vt1
Voltage on any pin relative to GND
Both
Vt2
Power dissipation
Both
PD
Storage temperature (plastic)
Both
Tstg
Ambient temperature with VCC
applied
Both
Tbias
–0.50
–0.50
–0.50
–
–65
–55
+7.0
V
+5.0
V
VCC +0.50
V
1.0
W
+150
°C
+125
°C
DC current into outputs (low)
Both
IOUT
–
20
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
WE
OE
LB
H
X
X
X
L
H
L
L
L
H
L
H
L
H
L
L
L
L
X
L
L
L
X
L
L
L
X
H
L
H
H
X
L
X
X
H
Key: H = High, L = Low, X = don’t care.
UB I/O0–I/O7 I/O8–I/O15
Mode
X
High Z
High Z
Standby (ISB), ISBI)
H
DOUT
High Z
Read I/O0–I/O7 (ICC)
L
High Z
DOUT
Read I/O8–I/O15 (ICC)
L
DOUT
DOUT
Read I/O0–I/O15 (ICC)
L
DIN
DIN
Write I/O0–I/O15 (ICC)
H
DIN
High Z
Write I/O0–I/O7 (ICC)
L
High Z
DIN
Write I/O8–I/O15 (ICC)
X
H
High Z
High Z
Output disable (ICC)
2/6/01; V.0.9
Alliance Semiconductor
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