MC80C86 Просмотр технического описания (PDF) - Intel

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MC80C86

16-BIT CHMOS MICROPROCESSOR

Intel 

M80C86 M80C86-2

Table 1 Pin Description (Continued)

The following pin function descriptions are for the M80C86 M82C88 system in maximum mode (i e

MN MX eVSS) Only the pin functions which are unique to maximum mode are described all other pin func-

tions are as described above

Symbol

S2 S1 S0

Pin No

26– 28

Type

O

Name and Function

STATUS active during T4 T1 and T2 and is returned to the passive

state (1 1 1) during T3 or during TW when READY is HIGH This

status is used by the M82C88 Bus Controller to generate all memory

and I O access control signals Any change by S2 S1 S0 during T4

is used to indicate the beginning of a bus cycle and the return to the

passive state in T3 or TW is used to indicate the end of a bus cycle

These signals float to 3-state OFF(1) in ‘‘hold acknowledge ’’ These

status lines are encoded as shown

RQ GT0

RQ GT1

30 31

S2

S1

S0

0 (LOW)

0

0

0

0

1

0

1

0

0

1

1

1 (HIGH)

0

0

1

0

1

1

1

0

1

1

1

Characteristics

Interrupt

Acknowledge

Read I O Port

Write I O Port

Halt

Code Access

Read Memory

Write Memory

Passive

I O REQUEST GRANT pins are used by other local bus masters to

force the processor to release the local bus at the end of the

processor’s current bus cycle Each pin is bidirectional with RQ GT0

having higher priority than RQ GT1 RQ GT has an internal pull-up

resistor so may be left unconnected The request grant sequence is

as follows (see timing diagram)

1 A pulse of 1 CLK wide from another local bus master indicates a

local bus request (‘‘hold’’) to the M80C86 (pulse 1)

2 During a T4 or T1 clock cycle a pulse 1 CLK wide from the

M80C86 to the requesting master (pulse 2) indicates that the

M80C86 has allowed the local bus to float and that it will enter the

‘‘hold acknowledge’’ state at the next CLK The CPU’s bus interface

unit is disconnected logically from the local bus during ‘‘hold

acknowledge ’’

3 A pulse 1 CLK wide from the requesting master indicates to the

M80C86 (pulse 3) that the ‘‘hold’’ request is about to end and that

M80C86 can reclaim the local bus at the next CLK

Each master-master exchange of the local bus is a sequence of 3

pulses There must be one dead CLK cycle after each bus exchange

Pulses are active LOW

If the request is made while the CPU is performing a memory cycle it

will release the local bus during T4 of the cycle when all the following

conditions are met

1 Request occurs on or before T2

2 Current cycle is not the low byte of a word (on an odd address)

3 Current cycle is not the first acknowledge of an interrupt

acknowledge sequence

4 A locked instruction is not currently executing

4

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