datasheetbank_Logo
Технический паспорт Поисковая и бесплатно техническое описание Скачать

M67025E(2007) Просмотр технического описания (PDF) - Atmel Corporation

Номер в каталоге
Компоненты Описание
Список матч
M67025E
(Rev.:2007)
Atmel
Atmel Corporation Atmel
M67025E Datasheet PDF : 27 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Using
Semaphores –
Some Examples
M67025E
Semaphore initialization is not automatic and must therefore be incorporated in the power up ini-
tialization procedures. Since any semaphore flag containing a zero must be reset to one,
initialization should write a one to all request flags from both sides to ensure that they will be
available when required.
Perhaps the simplest application of semaphores is their use as resource markers for the
M67025E’s dual-port RAM. If it is necessary to split the 8 Kb × 16 RAM into two 4 Kb × 16 blocks
which are to be dedicated to serving either the left or right port at any one time. Semaphore 0 can be
used to indicate which side is controlling the lower segment of memory and semaphore 1 can be defined
as indicating the upper segment of memory.
To take control of a resource, in this case the lower 4 Kb of a dual-port RAM, the left port proces-
sor would then write a zero into semaphore flag 0 and then read it back. If successful in taking
the token (reading back a zero rather than a one), the left processor could then take control of
the lower 4 Kb of RAM. If the right processor attempts to perform the same function to take con-
trol of the resource after the left processor has already done so, it will read back a one in
response to the attempted write of a zero into semaphore 0. At this point the software may
choose to attempt to gain control of the second 4 Kb segment of RAM by writing and then read-
ing a zero in semaphore 1. If successful, it will lock out the left processor.
Once the left side has completed its task it will write a one to semaphore 0 and may then attempt
to access semaphore 1. If semaphore 1 is still occupied by the right side, the left side may aban-
don its semaphore request and perform other operations until it is able to write and then read a
zero in semaphore 1. If the right processor performs the same operation with semaphore 0, this
protocol would then allow the two processes to swap
4 Kb blocks of dual-port RAM between one another.
The blocks do not have to be any particular size, and may even be of variable size depending on
the complexity of the software using the semaphore flags. All eight semaphores could be used
to divide the dual-port RAM or other shared resources into eight parts. Semaphores can even be
assigned different meanings on each side, rather than having a common meaning as is
described in the above example.
Semaphores are a useful form of arbitration in systems such as disk interfaces where the CPU
must be locked out of a segment of memory during a data transfer operation, and the I/0 device
cannot tolerate any wait states. If semaphores are used, both the CPU and the I/0 device can
access assigned memory segments, without the need for wait states, once the two devices have
determined which memory area is barred to the CPU.
Semaphores are also useful in applications where no memory WAIT state is available on one or
both sides. On a semaphore handshake has been performed, both processors can access their
assigned RAM segments at full speed.
Another application is in complex data structures. Block arbitration is very important in this case,
since one processor may be responsible for building and updating a data structure whilst the
other processor reads and interprets it. A major error condition may be created if the interpreting
processor reads an incomplete data structure. Some sort of arbitration between the two different
processors is therefore necessary. The building processor requests access to the block, locks it
and is then able to enter the block to update the data structure. Once the update is completed
the data structure may be released.
This allows the interpreting processor, to return to read the complete data structure, thus ensur-
ing a consistent data structure.
7
4146N–AERO–04/07

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]