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LZ21N3VS Просмотр технического описания (PDF) - Sharp Electronics

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LZ21N3VS Datasheet PDF : 18 Pages
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LZ21N3V/VS
PIN DESCRIPTION
SYMBOL
OD
OS
ØRS
ØV1A, ØV1B, ØV2, ØV3A, ØV3B, ØV4
ØH1, ØH2
OFD
PW
GND
NC1, NC2, NC3, NC4, NC5
PIN NAME
Output transistor drain
Output signals
Reset transistor clock
Vertical shift register clock
Horizontal shift register clock
Overflow drain
P-well
Ground
No connection
ABSOLUTE MAXIMUM RATINGS
(TA = +25 ˚C)
PARAMETER
SYMBOL
RATING
UNIT NOTE
Output transistor drain voltage
VOD
0 to +15
V
Overflow drain voltage
VOFD
Internal output
V
1
Reset gate clock voltage
VØRS
Internal output
V
2
Vertical shift register clock voltage
VØV
VPW to +15
V
Horizontal shift register clock voltage
VØH
–0.3 to +12
V
Voltage difference between P-well and vertical clock VPW-VØV
–24 to 0
V
Voltage difference between vertical clocks
VØV-VØV
0 to +15
V
3
Storage temperature
TSTG
–40 to +85
˚C
Ambient operating temperature
TOPR
–20 to +70
˚C
NOTES :
1. Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock is
applied below 22 Vp-p.
2. Do not connect to DC voltage directly. When ØRS is connected to GND, connect VOD to GND. Reset gate clock is
applied below 8 Vp-p.
3. When clock width is below 10 µs, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be
below 22 V.
2

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