GLT6100L08LL-70ST Просмотр технического описания (PDF) - G-Link Technology
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GLT6100L08LL-70ST Datasheet PDF : 10 Pages
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G-LINK
GLT6100L08
Ultra Low Power 128k x 8 CMOS SRAM
Nov 2000(Rev. 02)
Data Retention Waveform (TA = -25°C to 85°C)
Vcc
2.7V
tCDR
Data Retention Mode
VDR >= 1.0V
CE
VIH
VDR
2.7V
tR
VIH
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input and Output Timing
Reference Level
0.6V to 2.2V
5 ns
1.4V
Output Load Condition
70ns / 85ns
Load 100ns / 120ns
CL = 30pf + 1TTL Load
CL = 100pf + 1TTL Load
AC Test Loads and Waveforms
TTL
CL*
*Including Scope and Jig Capacitance
Read Cycle (3,9)( Vcc=2.7V to 3.3V, TA =-25°C to 85°C )
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold from address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Power-Up Time
Power-Down Time
55
Symbol
Min Max
tRC
55
tAA
55
tACE
55
tOE
35
tOH
10
tCLZ
10
tCHZ
25
tOLZ
5
tOHZ
25
tPU
0
tPD
55
70
Min Max
70
70
70
40
10
10
30
5
25
0
70
85
Min Max
85
85
85
40
10
10
35
5
30
0
85
100
Min Max
100
100
100
50
10
10
40
5
35
0
100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
4,5
3,4,5
4,5
3,4,5
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
-4-
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
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