M37516ED-XXXHP Просмотр технического описания (PDF) - Renesas Electronics
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M37516ED-XXXHP Datasheet PDF : 90 Pages
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7516 Group
TIMING REQUIREMENTS
Table 29 Timing requirements (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 clock input set up time
Serial I/O1 clock input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input set up time
Serial I/O2 clock input hold time
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Table 30 Timing requirements (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
tW(RESET)
Reset input “L” pulse width
tC(XIN)
External clock input cycle time
tWH(XIN)
External clock input “H” pulse width
tWL(XIN)
External clock input “L” pulse width
tC(CNTR)
CNTR0, CNTR1 input cycle time
tWH(CNTR)
CNTR0, CNTR1 input “H” pulse width
tWL(CNTR)
CNTR0, CNTR1 input “L” pulse width
tWH(INT)
INT0 to INT3 input “H” pulse width
tWL(INT)
INT0 to INT3 input “L” pulse width
tC(SCLK1)
Serial I/O1 clock input cycle time (Note)
tWH(SCLK1)
Serial I/O1 clock input “H” pulse width (Note)
tWL(SCLK1)
Serial I/O1 clock input “L” pulse width (Note)
tsu(RxD-SCLK1) Serial I/O1 clock input set up time
th(SCLK1-RxD)
Serial I/O1 clock input hold time
tC(SCLK2)
Serial I/O2 clock input cycle time
tWH(SCLK2)
Serial I/O2 clock input “H” pulse width
tWL(SCLK2)
Serial I/O2 clock input “L” pulse width
tsu(SIN2-SCLK2) Serial I/O2 clock input set up time
th(SCLK2-SIN2)
Serial I/O2 clock input hold time
Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Min.
20
125
50
50
200
80
80
80
80
800
370
370
220
100
1000
400
400
200
200
Limits
Typ.
Max.
Unit
XIN cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min.
20
250
100
100
500
230
230
230
230
2000
950
950
400
200
2000
950
950
400
300
Limits
Typ.
Max.
Unit
XIN cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev.1.01 Jul 01, 2003 page 83 of 89
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