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M37516E6HP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Renesas Electronics 

7516 Group

b7

b0

I2C START/STOP condition

SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0 control register

(S2D : address 003016)

START/STOP condition set bit

SCL/SDA interrupt pin polarity

selection bit

0 : Falling edge active

1 : Rising edge active

SCL/SDA interrupt pin selection bit

0 : SDA valid

1 : SCL valid

Reserved

Do not write “1” to this bit.

Fig. 38 Structure of I2C START/STOP condition control register

Table 12 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency

Oscillation

frequency

f(XIN) (MHz)

Main clock

divide ratio

System

clock φ

(MHz)

8

2

4

8

8

1

4

2

2

2

2

1

START/STOP

condition

control register

XXX11010

XXX11000

XXX00100

XXX01100

XXX01010

XXX00100

SCL release time

(µs)

6.75 µs (27 cycles)

6.25 µs (25 cycles)

5.0 µs (5 cycles)

6.5 µs (13 cycles)

5.5 µs (11 cycles)

5.0 µs (5 cycles)

Setup time

(µs)

3.375 µs (13.5 cycles)

3.125 µs (12.5 cycles)

2.5 µs (2.5 cycles)

3.25 µs (6.5 cycles)

2.75 µs (5.5 cycles)

2.5 µs (2.5 cycles)

Hold time

(µs)

3.375 µs (13.5 cycles)

3.125 µs (12.5 cycles)

2.5 µs (2.5 cycles)

3.25 µs (6.5 cycles)

2.75 µs (5.5 cycles)

2.5 µs (2.5 cycles)

Note: Do not set an odd number to the START/STOP condition set bit (SSC4 to SSC0).

(1) A master-transmitter transnmits data to a slave-receiver

S Slave address R/W A Data A Data A/A P

7 bits

“0”

1 to 8 bits

1 to 8 bits

(2) A master-receiver receives data from a slave-transmitter

S Slave address R/W A Data A Data A P

7 bits

“1”

1 to 8 bits

1 to 8 bits

(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address

S

Slave address

1st 7 bits

R/W

A

Slave address

2nd bytes

A

Data A

Data A/A P

7 bits

“0”

8 bits

1 to 8 bits

1 to 8 bits

(4) A master-receiver receives data from a slave-transmitter with a 10-bit address

S

Slave address

1st 7 bits

R/W

Slave address

A 2nd bytes

A

Sr

Slave address

1st 7 bits

R/W

A

Data A

Data A P

7 bits

“0”

8 bits

7 bits

“1”

1 to 8 bits

1 to 8 bits

S : START condition

A : ACK bit

Sr : Restart condition

P : STOP condition

R/W : Read/Write bit

Fig. 39 Address data communication format

: Master to slave

: Slave to master

Rev.1.01 Jul 01, 2003 page 37 of 89

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