M37640E8FP Просмотр технического описания (PDF) - Mitsumi
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M37640E8FP Datasheet PDF : 96 Pages
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Ver 1.4
1.10 CPU MODE REGISTERS
This device has two CPU mode registers:
• CPU Mode Register A (CPMA)
• CPU Mode Register B (CPMB)
These registers control the processor mode, clock,
slow memory wait and other CPU functions. The bit
representation of each register is described in Figure
1.5 and Figure 1.6.
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MSB
7
CPMA7
CPMA6 CPMA5
CPMA4 Reserved
CPMA2
CPMA1
CPMA0
LSB
0
Address: 000016
Access: R/W
Reset: OC16
CPMA0,1
CPMA2
CPMA3
CPMA4
CPMA5
CPMA6
CPMA7
Processor Mode Bits (bits 1,0)
Bit 1
Bit 0
0
0: Single-Chip Mode
0
1: Memory Expansion Mode
1
0: Microprocessor Mode
1
1: Not Used
Stack Page Selection Bit (bit 2)
0: In page 0 area
1: In page 1 area
Reserved (Read/Write “1”)
Clock XCin - XCout Stop Bit (bit 4)
0: Stop
1: Oscillator
Clock Xin - Xout Stop Bit (bit 5)
0: Oscillator
1: Stop
Internal Clock Selection Bit (bit 6)
0: External Clock
1: fsyn
External Clock Selection Bit (bit 7)
0: Xin - Xout
1: XCin - XCout
Fig. 1.5. CPU Mode Register A (CPMA)
MSB
7
Reser ved
Reserved
CPMB5
CPMB4
CPMB3
CPMB2
CPMB1
CPMB0
LSB
0
Address: 000116
Access: R/W
Reset: 8316
CPMB0,1
CPMB2,3
CPB4
CPMB5
CPMB6
CPMB7
Slow Memory Wait Bits (bits 1,0)
Bit 1
Bit 0
0
0: No Wait
0
1: One time wait
1
0: Two time wait
1
1: Three time wait
Slow Memory Mode Bit (bit 3,2)
Bit 3
Bit 2
0
0: Software wait
0
1: Not used
1
0: Fixed wait by RDY pin L
1
1: Extended RDY wait
Expanded Data Memory Access Bit (bit 4)
0:EDMA output disabled (64 Kbyte data access area)
1:EDMA output enabled (greater than 64 Kbytes data access area)
Hold Function Enable Bit (bit 5)
0:HOLD Function Disabled
1:HOLD Function Enabled
Reserved (Read/Write “0”)
Reserved (Read/Write “1”)
Fig.1.6. CPU Mode Register B (CPMB)
7
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