M37516 Просмотр технического описания (PDF) - Mitsumi

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M37516

Single chip 8-bit microcomputer

Mitsumi 

INTERRUPTS

Interrupts occur by 17 sources among 17 sources: seven external,

nine internal, and one software.

Interrupt Control

Each interrupt is controlled by an interrupt request bit, an interrupt

enable bit, and the interrupt disable flag except for the software in-

terrupt set by the BRK instruction. An interrupt occurs if the

corresponding interrupt request and enable bits are “1” and the in-

terrupt disable flag is “0”.

Interrupt enable bits can be set or cleared by software.

Interrupt request bits can be cleared by software, but cannot be

set by software.

The BRK instruction cannot be disabled with any flag or bit. The I

(interrupt disable) flag disables all interrupts except the BRK in-

struction interrupt.

When several interrupts occur at the same time, the interrupts are

received according to priority.

Interrupt Operation

By acceptance of an interrupt, the following operations are auto-

matically performed:

1. The contents of the program counter and the processor status

register are automatically pushed onto the stack.

2. The interrupt disable flag is set and the corresponding interrupt

request bit is cleared.

3. The interrupt jump destination address is read from the vector

table into the program counter.

sNotes

When the active edge of an external interrupt (INT0–INT3, SCL/

SDA, CNTR0, CNTR1) is set, the corresponding interrupt request

bit may also be set. Therefore, take the following sequence:

1. Disable the interrupt

2. Change the interrupt edge selection register

(SCL/SDA interrupt pin polarity selection bit for SCL/SDA; the

timer XY mode register for CNTR0 and CNTR1)

3. Clear the interrupt request bit to “0”

4. Accept the interrupt.

M37516M6-XXXHP

GNOK-M37516M6-XXXHP-50

(MSETSU 2)

PA

GE

12/54

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