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M30240M6

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Mitsumi 

Preliminary Specifications REV. E

Specifications in this manual are tentative and subject to change

Mitsubishi microcomputers

M30240 Group

Central Processing Unit (CPU)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2.1.8.7 Bit 6: Interrupt enable flag (I flag)

This flag enables a maskable interrupt.

An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0”

when the interrupt is acknowledged.

2.1.8.8 Bit 7: Stack pointer select flag (U flag)

Interrupt stack pointer (ISP) is selected when this flag is “0”; user stack pointer (USP) is selected when this

flag is “1”.

This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software inter-

rupts 0 to 31 is executed.

2.1.8.9 Bits 8 to 11: Reserved area

2.1.8.10 Bits 12 to 14: Processor interrupt priority level (IPL)

Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor

interrupt priority levels from level 0 to level 7.

If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is en-

abled.

2.1.8.11 Bit 15: Reserved area

The C, Z, S, and O flags are changed when instructions are executed. See the M16C software manual

for details.

b15

IPL

b0

U I O B S Z D C Flag register (FLG)

Carry flag

Debug flag

Zero flag

Sign flag

Register bank select flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

Reserved area

Figure 1.6: Flag register (FLG)

1-13

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