27C512-120 Просмотр технического описания (PDF) - STMicroelectronics

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27C512-120

512 Kbit (64Kb x8) UV EPROM and OTP EPROM

STMicroelectronics 

M27C512

Figure 7. Programming and Verify Modes AC Waveforms

A0-A15

Q0-Q7

VCC

GVPP

E

tAVEL

DATA IN

tQVEL

VALID

tEHQX

tVCHEL

tVPHEL

tEHVPX

tVPLEL

tELEH

PROGRAM

DATA OUT

tELQV

tEHAX

tEHQZ

VERIFY

AI00737

Figure 8. Programming Flowchart

VCC = 6.25V, VPP = 12.75V

SET MARGIN MODE

n=0

NO

++n

= 25

YES

E = 100µs Pulse

NO

VERIFY

YES

++ Addr

FAIL

Last NO

Addr

YES

RESET MARGIN MODE

CHECK ALL BYTES

1st: VCC = 6V

2nd: VCC = 4.2V

AI00738B

10/18

PRESTO IIB Programming Algorithm

PRESTO IIB Programming Algorithm allows the

whole array to be programmed with a guaranteed

margin, in a typical time of 6.5 seconds. This can

be achieved with STMicroelectronics M27C512

due to several design innovations described in the

M27C512 datasheet to improve programming effi-

ciency and to provide adequate margin for reliabil-

ity. Before starting the programming the internal

MARGIN MODE circuit is set in order to guarantee

that each cell is programmed with enough margin.

Then a sequence of 100µs program pulses are ap-

plied to each byte until a correct verify occurs. No

overprogram pulses are applied since the verify in

MARGIN MODE provides the necessary margin.

Program Inhibit

Programming of multiple M27C512s in parallel

with different data is also easily accomplished. Ex-

cept for E, all like inputs including GVPP of the par-

allel M27C512 may be common. A TTL low level

pulse applied to a M27C512’s E input, with VPP at

12.75V, will program that M27C512. A high level E

input inhibits the other M27C512s from being pro-

grammed.

Program Verify

A verify (read) should be performed on the pro-

grammed bits to determine that they were correct-

ly programmed. The verify is accomplished with G

at VIL. Data should be verified with tELQV after the

falling edge of E.

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