M25P10 Просмотр технического описания (PDF) - STMicroelectronics

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M25P10

1 Mbit Low Voltage Paged Flash Memory With 20 MHz Serial SPI Bus Interface

STMicroelectronics 

M25P10

Figure 15. DP: Enter Deep Power Down Mode Sequence

S

01234567

tDP

C

INSTRUCTION

D

Stand-by Power Down Mode Deep Power Down Mode

AI03753

sets the Write Enable Latch (WEL) which allows

the execution of any further Bulk Erase. The Bulk

Erase instruction is entered by driving the Chip

select input (S) low, followed by the instruction

byte on Data In input (D).

The Chip Select input (S) must be driven low for

the entire duration of the sequence. The device

must be deselected just after the eighth bit of the

instruction byte has been latched in. If not, the

Bulk Erase instruction is not executed. As soon as

the device is deselected, the self-timed Bulk Erase

cycle (tBE) is initiated. While the Bulk Erase cycle

is in progress, the status register may be read to

check the WIP bit value. WIP is high during the

self-timed Bulk Erase cycle and is low when it is

completed. When the cycle is completed, the write

enable latch (WEL) is reset.

The Bulk Erase instruction is internally taken into

account if, and only if, (BP0, BP1) = (0,0). In other

words, the Bulk Erase instruction is ignored if at

least one Sector is software protected. In this case

the Bulk Erase instruction is discarded and none of

the Sectors are erased.

The timing sequence is shown in Figure 14.

Enter Deep Power Down Mode (DP)

After Power-on, when S is high, the memory is

deselected, the Q output pin is at high impedance

and the device is in the Standby Power Mode state

(ICC1). Under this state, the Memory waits for a

select condition and is able to receive, decode and

execute all instructions.This mode is not the Deep

Power Down Mode which is entered by the way of

a specific instruction. The purpose of the Deep

Power down mode is to drastically reduce the

standby current from ICC1 to ICC2 (see Table 10).

Once the device has entered the Deep Power

Down Mode, all instructions are ignored except the

RES instruction which releases the part from this

Figure 16. RES: Release from Deep Power Down Mode and Read Electronic Signature Sequence

S

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38

C

INSTRUCTION

24 BIT ADDRESS

D

23 22 21

3210

HIGH IMPEDANCE

Q

DATA OUT (Electronic Signature)

76543210

MSB

Deep Power Down Mode Stand-by Power Down Mode

AI03755

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