LXT310 Просмотр технического описания (PDF) - Level One
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LXT310 Datasheet PDF : 18 Pages
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The equalized signal is filtered and applied to the peak de-
tector and data slicers. The peak detector samples the in-
puts and determines the maximum value of the received
signal. A percentage of the peak value is provided to the
data slicers as a threshold level to ensure optimum signal-
to-noise ratio. The threshold is set to 50% of the peak val-
ue. The receiver is capable of accurately recovering signals
with up to 36 dB of cable attenuation (from 2.4 V)
After processing through the data slicers, the received sig-
nal is routed to the data and timing recovery section, then
to the B8ZS decoder (if selected) and to the LOS processor.
The LOS Processor loads a digital counter at the RCLK fre-
quency. The count is incremented each time a zero (space)
is received, and reset to zero each time a one (mark) is re-
ceived. Upon receipt of 175 consecutive zeros the LOS pin
goes High, and a smooth transition replaces the RCLK out-
put with the MCLK. (During LOS if MCLK is not supplied
and JASEL = 1, the RCLK output is replaced with the cen-
tered crystal clock.)
Received marks will be output regardless of the LOS sta-
tus, but the LOS pin will not reset until the ones density
reaches 12.5 %. This level is based on receipt of at least 4
ones in any 32-bit period.
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Input data (bipolar or unipolar) for transmission onto the
line is clocked serially into the device. Bipolar data is input
at pin 3 (TPOS) and pin 4 (TNEG). Unipolar data is input
at pin 3 (TDATA) only. (Unipolar mode is enabled by
holding pin 4 high for 16 RCLK cycles). Input data may be
passed through the Jitter Attenuator and/or B8ZS encoder,
if selected. In Host Mode, B8ZS is selected by setting bit
D3 of the input data byte. In Hardware Mode, B8ZS is
selected by connecting the MODE pin to RCLK. Input
synchronization is supplied by the transmit clock (TCLK).
Timing requirements for TCLK and the Master Clock
(MCLK) are defined in Test Specifications.
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LBO settings are input through the serial port in the Host
Mode. In the Hardware Mode, LBO inputs are applied
through individual pins. Shaped pulses meeting the vari-
ous T1 CSU and ISDN PRI requirements are applied to the
AMI line driver for transmission onto the line at TTIP and
TRING. Refer to Test Specifications for T1 pulse mask
specifications.
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The LXT310 transmits data as a 50% AMI line code as
shown in Figure 3. Power consumption is reduced by acti-
vating the AMI line driver only to transmit a mark. The
output driver is disabled during transmission of a space.
Biasing of the transmit DC level is on-chip.
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