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LX1692B

Full Bridge Resonant CCFL Controller

Microsemi Corporation 

LX1692B

TM

®

Full Bridge Resonant CCFL Controller

PRODUCTION DATA SHEET

FUNCTIONAL DESCRIPTION (CONTINUED)

INTERMITTENT OR BROKEN LAMP AFTER SUCCESSFUL

IGNITION

After run mode is entered, an intermittent or open lamp

problem can also be detected at the ISNS input. After

ignition, peak voltage on the ISNS input is dependent on

lamp current amplitude and voltage on the BRITE_A pin.

I_SNS signal amplitude should be designed to be greater

than +/- 400 mVPK (280 mVRMS) to insure a false open

lamp fault shut down does not occur. A comparator

monitors ISNS and generates a reset pulse to a watch dog

timer for any peak voltage > 0.3V. The watch dog, a 9 bit

binary counter, is reset once every cycle of I_SNS voltage.

If lamp current flowing through the ISNS resistor is too low

(e.g., voltage is less than 0.3V peak), reset pulses are not

generated and the counter is allowed to overflow and set the

fault latch. Nominal short circuit duration is 500 micro

seconds when operating at 65 KHz.

ON CHIP LDO REGULATOR

Output voltage is 4.0 +/-5%. Supplies all internal circuitry

except output driver stage. Capable to source 5mA to

external circuitry.

SHORT CIRCUITS ACROSS THE LAMP TERMINALS,

SHORTS FROM THE HIGH VOLTAGE TERMINAL TO

GROUND AND SHORT CIRCUITS FROM GROUND TO THE

LOW SIDE LAMP TERMINAL.

A Short to ground from the lamp return terminal also

shorts out the lamp current sense resistor, removing current

feedback to the controller. This short is detected as a rise

in voltage across the OC_SNS resistor which is located on

the normally grounded side of the HV transformer

secondary. A comparator senses peak voltage > 2.0Vdc at

the OC_SNS pin. This comparator clocks the 4 bit watch

dog timer described above in the open lamp fault logic.

Sixteen events during a single cycle of the C_BST signal

will overflow the watchdog counter and cause an over

current shut down during either strike or run mode.

UNDER VOLTAGE LOCKOUT

Keeps chip outputs active off until VDDA is high enough

to insure stable operation.

DIMMING MODES

Separate input pins are available for digital and analog

dimming modes for maximum flexibility. See dimming

truth table below. Digital dimming rise and fall times can

be controlled by the ICOMP capacitor (See Dimming

Modes Table).

DIMMING MODES

MODE

BRITE A BRITE D

ISNS

CBST I Range

DC voltage controlled analog

0 – 2V

VDDA

cap

3:1

External PWM controlled digital

VDDA

PWM

cap

60:1

DC voltage controlled digital

VDDA

0.5-2.5V

Cap

30:1

Analog + voltage controlled Digital

0 -2V

0.5-2.5V

Cap

60:1

Note: For Reverse analog dimming, BRITE_A signal inversion must occur external to the controller

Copyright © 2005

Rev. 1.1, 12/20/2006

Microsemi

Integrated Products Division

11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570

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