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LX1691
(Rev.:2004)

Enhanced Multi-Mode CCFL Controller

Microsemi Corporation 

LX1691

TM

®

Enhanced Multi-Mode CCFL Controller

PRODUCTION DATA SHEET

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (VDDP) ..................................................................................................... 6V

Digital Input (ENABLE)....................................................................... -0.3V to VDDP +0.5V

Analog Inputs (I_SNS, OC_SNS, OV_SNS)clamped to +/- 10V. Max peak current +/-100mA

Analog Inputs (BRITE_IN)................................................................... -0.3V to VDDP +0.5V

DIM_MODE Input ................................................................................ -0.3V to VDDP +0.5V

DD_CLK Digital Input ........................................................................ 0.3V to VDDP +0.5V

Digital Output (AOUT, BOUT) .................................................................. -0.3V to VDDP +0.5V

Analog Outputs (BRITE_R, I_R, EA_OUT,BRITE_OUT) ....................... -0.3V to VDDP +0.5V

Operating Temperature Range ........................................................................ -55 to 125°C

Maximum Junction Temperature ...............................................................................150°C

Package Peak Temperature for Solder Reflow (40 Seconds Maximum Exposure) ......... 255°C (+5 -0)

Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to

Ground. Currents are positive into, negative out of specified terminal.

PACKAGE PIN OUT

GND

1

AOUT

2

BOUT

3

DIM_CLK

4

DIM_MODE

5

BRITE_OUT

6

BRITE_R

7

BRITE_IN

8

16

VDDP

15

VDDA

14

OP_SNS

13

VIN_SNS

12

I_SNS

11

EA_OUT

10

I_R

9

ENABLE

PW PACKAGE

(Top View)

Pb-free 100% Matte Tin Lead Finish

THERMAL DATA

PW Plastic TSSOP 16-Pin

THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA

99°C/W

Junction Temperature Calculation: TJ = TA + (PD x θJA).

The θJA numbers are guidelines for the thermal performance of the device/pc-board

system. All of the above assume no ambient airflow.

PIN NAME

GND

VDDP

VDDA

AOUT

BOUT

DD_CLK*

FUNCTIONAL PIN DESCRIPTION

DESCRIPTION

Ground

Voltage Input, 3.0 to 5.5V input range. VDDP is switched (see ENABLE) to remove power from chip. An LDO

regulator follows the switch and generates VDDA (see VDDA). The output driver stages are powered directly from

the VDDP input. Care must be taken in power distribution design to minimize transients and noise coupling from

VDDP to the VDDA output.

Analog VDDA Supply Output. This output pin is used to connect an external capacitor to stabilize and filter the on

chip VDDA LDO regulator. The input of the LDO is the switched VDDP supply. LDO output is normally 3.0V and is

used to drive all circuitry except the output buffers at AOUT and BOUT. Drop out voltage is typically 50mV (@

25°C) at 5mA, the average internal load. This output can supply up to a 5 mA external load. The output

capacitor recommended is <1000nF of the ceramic dielectric type.

A buffer N-FET driver output. 10K internal pull down, ± 100 mA peak current with 3 VDC applied to VDDP pin.

B buffer N-FET driver output. 10K internal pull down, ± 100 mA peak current with 3 VDC applied to VDDP pin.

Digital Dimming Clock / Dimming Polarity. An input pin that may be selected to control burst frequency for Digital

Dimming. This input can be forced to VDDA or VSS or any clock signal up to 1MHz. This pin is also used to

control the dimming polarity when operating in the internally clocked digital dimming mode*. If DIM_MODE is in

the open condition (Analog Dimming Mode) the DD_CLK input is tied to VDDA or open (internal pull-up) to select

conventional dimming polarity. It is tied to Ground for reverse polarity. Conventional polarity means that lamp

brightness increases with increasing voltage on the BRITE_IN pin. Reverse polarity means that brightness

decreases with increasing voltage. If DIM_MODE is open and a low frequency pulse is applied to DD_CLK, lamp

current amplitude is directly proportional to the voltage at BRITE_IN, and its duty cycle follows the DD_CLK

waveform, e.g., current flows when DD_CLK is high. In this mode pulse count should be greater than fault

count..

Copyright © 2003

Rev. 1.0, 7/16/2004

Microsemi

Integrated Products

11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570

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