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LTC4311IDC Просмотр технического описания (PDF) - Linear Technology

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LTC4311IDC
Linear
Linear Technology Linear
LTC4311IDC Datasheet PDF : 12 Pages
First Prev 11 12
LTC4311
PACKAGE DESCRIPTION
DC Package
6-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1703)
0.675 ±0.05
R = 0.115
TYP
0.56 ± 0.05
4
(2 SIDES)
0.38 ± 0.05
6
2.50 ±0.05
1.15
±0.05
0.61 ±0.05
(2 SIDES)
PACKAGE PIN 1 BAR
OUTLINE TOP MARK
(SEE NOTE 6)
0.25 ± 0.05
0.50 BSC
1.42 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.200 REF
2.00 ±0.10
(4 SIDES)
0.75 ±0.05
0.00 – 0.05
PIN 1
CHAMFER OF
EXPOSED PAD
3
1
(DC6) DFN 1103
0.25 ± 0.05
0.50 BSC
1.37 ±0.05
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE
M0-229 VARIATION OF (WCCD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.47
MAX
2.8 BSC 1.8 REF
SC6 Package
6-Lead Plastic SC70
(Reference LTC DWG # 05-08-1638 Rev B)
0.65
REF
1.00 REF
1.80 – 2.20
(NOTE 4)
1.80 – 2.40
1.15 – 1.35
(NOTE 4)
INDEX AREA
(NOTE 6)
PIN 1
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.10 – 0.40
GAUGE PLANE
0.15 BSC
0.26 – 0.46
0.10 – 0.18
NOTE:
(NOTE 3)
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
0.65 BSC
0.80 – 1.00
1.00 MAX
0.15 – 0.30
6 PLCS (NOTE 3)
0.00 – 0.10
REF
SC6 SC70 1205 REV B
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. DETAILS OF THE PIN 1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE INDEX AREA
7. EIAJ PACKAGE REFERENCE IS EIAJ SC-70
8. JEDEC PACKAGE REFERENCE IS MO-203 VARIATION AB
4311fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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