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LTC4309CGN-PBF

Level Shifting Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery

Linear Technology 

LTC4309

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, VCC2 = 3.3V, unless otherwise noted.

SYMBOL

VTHR(HYST)

CIN

ILEAK

VOL

PARAMETER

SDA, SCL Logic Input Threshold Voltage

Hysteresis

Digital Input Capacitance SDAIN,

SDAOUT, SCLIN, SCLOUT

Input Leakage Current

Output Low Voltage

VILMAX

Buffer Input Logic Low Voltage

Bus Stuck Low Timeout

CONDITIONS

(Note 3)

(Note 3)

SDA, SCL, ACC, DISCEN Pins

SDA, SCL Pins, ISINK = 4mA, Driven SDA/SCL = 0.2V, VCC =

VCC2 = 2.7V

2.7k to VCC on SDA, SCL, Driven SDA/SCL = 0.1V,

VCC = VCC2 = 3.3V

MIN TYP MAX UNITS

50

mV

10 pF

l

l0

±5 μA

0.4

V

l 120 170 205 mV

l

1.2

V

tTIMEOUT

VOL_FAULT

IOFF_FAULT

Bus Stuck Low Timer

FAULT Output Low Voltage

FAULT Off Leakage Current

SDAOUT, SCLOUT = OV

IFAULT = 3mA

l 25 30 35 ms

l

0.4

V

l

0.1 ±5 μA

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Test performed with connection circuity active.

Note 3: Determined by design, not subject to test.

Note 4: For larger equivalent bus capacitance, the skew increases, and

setup and hold times must be adjusted accordingly. Please see the

Operation Section of the datasheet.

Note 5: Measure points are 0.3 • VCC and 0.7 • VCC.

Note 6: All currents into pins are positive, all voltages are referenced to

GND, unless otherwise specified.

Note 7: IPULLUPAC varies with temperature and VCC voltage as shown in the

Typical Performance Characteristics section.

TIMING DIAGRAMS

ENABLE and READY Timing

tPLH_READY

tPLH_EN

ENABLE

tPHL_READY

tPHL_EN

CONNECT

SDAIN/SCLIN

READY

4309 TD01

SDA/SCL Propagation Delays, Rise and Fall Times

tRISE

tPLH

tPHL tRISE

tFALL

SDAOUT/SCLOUT

4

Figure 1. Timing Diagrams

tFALL

4309 TD02

4309fa

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