LTC4218CGN(RevB) Просмотр технического описания (PDF) - Linear Technology
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LTC4218CGN Datasheet PDF : 16 Pages
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LTC4218
APPLICATIONS INFORMATION
After the 1.2ms timeout the FLT pin needs to pull down on
the UV pin to restart the power-up sequence.
Since the default values for overvoltage, undervoltage and
powergood thresholds for the 12V fixed version match
the requirements, no external components are required
for the UV, OV and FB pins.
The final schematic results in very few external com-
ponents. Resistor R1 (10Ω) prevents high frequency
oscillations in Q1 while RGATE of 1k isolates CGATE during
fast turn-off. The pull-up resistor, (R2), connects to the
PG pin while the 20k (R3) converts the IMON current to a
voltage at a ratio:
VIMON
=
6.67µA
mV
•
2mV
A
•
20k
=
0.267V
A
In addition, there is a 0.1μF bypass (C1) on the INTVCC
pin.
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
for the sense resistor is recommended. The PCB layout
should be balanced and symmetrical to minimize wiring
errors. In addition, the PCB layout for the sense resistors
and the power MOSFETs should include good thermal
management techniques for optimal device power dissipa-
tion. A recommended PCB layout for the sense resistor
and power MOSFET is illustrated in Figure 6.
In Hot Swap applications where load currents can be 6A,
narrow PCB tracks exhibit more resistances than wider
tracks and operate at elevated temperatures. The minimum
trace width for 1oz copper foil is 0.02” per amp to make sure
the trace stays at a reasonable temperature. Using 0.03”
per amp or wider is recommended. Note that 1oz copper
exhibits a sheet resistance of about 0.5mΩ/square. Small
resistances add up quickly in high current applications
It is also important to put C1, the bypass capacitor for the
INTVCC pin, as close as possible between the INTVCC and
GND. Place the 10Ω resistor as close as possible to Q1.
This will limit the parasitic trace capacitance that leads to
Q1 self-oscillation.
Additional Applications
The LTC4218 has a wide operating range from 2.9V to
26.5V. The UV, OV and PG thresholds are set with a few
resistors. All other functions are independent of supply
voltage.
The last page includes a 24V application with a UV threshold
of 19.8V, an OV threshold of 28.3V and a PG threshold
of 20.75V. Figure 7 shows a 3.3V application with a UV
threshold of 2.87V, an OV threshold of 3.77V and a PG
threshold of 3.05V.
Q1
RS
R1
LTC4218
C
4218 F06
Figure 6. Recommended Layout
RS
2mΩ
Q1
Si7104DN
VOUT
3.3V
3.3V
6A
R1
R5
+
CL
10Ω
14.7k
330μF
R2
17.4k
R3
3.16k
R4
10k
CT
0.1μF
C1
0.1μF
SENSE– GATE SOURCE
SENSE+
RGATE
1k
CGATE
0.01μF
VDD
FB
UV
R6
3.3V
10k
FLT LTC4218GN
OV
R7
10k
PG
TIMER
INTVCC
GND
IOUT
RMON
20k
ADC
4218 F07
Figure 7. 3.3V, 6A Card Resident Application
4218fb
14
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